公开(公告)号：US10797018B2

公开(公告)日：2020-10-06

申请号：US16392221

申请日：2019-04-23

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano

IPC: H01L23/02 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L21/78 ,  H01L21/683

Abstract: Methods of forming semiconductor device packages comprising stacking multiple dice, the die stack exhibiting thin bond lines and having an outer environmental coating, the bond lines and environmental coating comprising an in situ formed compound. Semiconductor device packages so formed and electronic systems incorporating such packages are also disclosed.

公开(公告)号：US20200211996A1

公开(公告)日：2020-07-02

申请号：US16236687

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Mark E. Tuttle

IPC: H01L23/00 ,  H01L25/065

Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.

公开(公告)号：US20200211967A1

公开(公告)日：2020-07-02

申请号：US16236681

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano

IPC: H01L23/538 ,  H01L25/11 ,  H01L23/532

Abstract: Semiconductor device packages include a redistribution layer (RDL) with carbon-based conductive elements. The carbon-based material of the RDL may have low electrical resistivity and may be thin (e.g., less than about 0.2 μm). Adjacent passivation material may also be thin (e.g., less than about 0.2 μm). Methods for forming the semiconductor device packages include forming the carbon-based material (e.g., at high temperatures (e.g., at least about 550° C.)) on an initial support wafer with a sacrificial substrate. Later or separately, components of a device region of the package may be formed and then joined to the initial support wafer before the sacrificial substrate is removed to leave the carbon-based material joined to the device region.

公开(公告)号：US10446527B2

公开(公告)日：2019-10-15

申请号：US16128414

申请日：2018-09-11

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/522

Abstract: Semiconductor devices, systems including semiconductor devices, and methods of making and operating semiconductor devices. Such semiconductor devices can comprise a substrate, a first die mounted to the substrate, and a second die mounted to the first die in an offset position. The first die having first inductors at a first active side of the first die, the second inductors at a second active side of the second die, and a least one first inductor is proximate and inductively coupled to a second inductor. First interconnects electrically couple the substrate to the first die, and second interconnects electrically couple the second die to the substrate. The first interconnects extend from an upper surface of the substrate to the first active side, and the second interconnects extend from the second active side to the lower surface of the substrate.

公开(公告)号：US12199068B2

公开(公告)日：2025-01-14

申请号：US17817690

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Randon K. Richards ,  Aparna U. Limaye ,  Dong Soon Lim ,  Chan H. Yoo ,  Bret K. Street ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L25/065 ,  H01L21/66 ,  H01L21/78 ,  H01L23/00 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H01L25/00 ,  H01L25/18 ,  H01Q1/22 ,  H01Q1/48

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

公开(公告)号：US20240313098A1

公开(公告)日：2024-09-19

申请号：US18598735

申请日：2024-03-07

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin

IPC: H01L29/775 ,  H01L23/00 ,  H01L25/065 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L29/775 ,  H01L24/80 ,  H01L25/0657 ,  H01L27/0886 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696 ,  H01L2224/80895 ,  H01L2924/1436 ,  H10B12/01

Abstract: Methods, systems, and devices for transistor architectures in coupled semiconductor systems are described. A memory system may be formed from multiple semiconductor components (e.g., multiple dies, multiple wafers) that are coupled together, with different semiconductor components implementing different techniques for transistor formation. For example, a first die may include a memory array and first circuitry configured to access the memory array, and a second die coupled with the first die may include second circuitry configured to access the memory array. The first circuitry may include transistors formed in accordance with a first fabrication technique (e.g., to form a first type of transistors) and the second circuitry may include transistors formed in accordance with a second fabrication technique (e.g., to form a second type of transistors). The dies may be coupled in a manner that provides an electrical coupling between the first circuitry and the second circuitry.

公开(公告)号：US12051670B2

公开(公告)日：2024-07-30

申请号：US17490224

申请日：2021-09-30

Applicant: Micron Technology, Inc.

Inventor： Mark E. Tuttle ,  John F. Kaeding ,  Owen R. Fay ,  Eiichi Nakano ,  Shijian Luo

IPC: H01L23/49 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L24/29 ,  H01L24/33 ,  H01L2224/29078 ,  H01L2224/32105 ,  H01L2224/3303 ,  H01L2224/33107 ,  H01L2224/3313 ,  H01L2924/381

Abstract: A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.

公开(公告)号：US20240176523A1

公开(公告)日：2024-05-30

申请号：US18516734

申请日：2023-11-21

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin ,  Ameen D. Akel

IPC: G06F3/06 ,  G06F1/06

CPC classification number: G06F3/064 ,  G06F1/06 ,  G06F3/061 ,  G06F3/0683

Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of the circuitry configured to access the set of memory arrays, and a second die may include a second portion of the circuitry configured to access the set of memory arrays. The first portion and the second portion of the circuitry configured to access a set of memory arrays may be communicatively coupled between the dies using various interconnection techniques, such as a fusion of conductive contacts of the respective memory dies. In some examples, the second die may also include the host itself (e.g., a host processor).

公开(公告)号：US20240170435A1

公开(公告)日：2024-05-23

申请号：US18419382

申请日：2024-01-22

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Mark E. Tuttle

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/29 ,  H01L24/27 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/279 ,  H01L2224/29076 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2919 ,  H01L2224/83851

Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.

公开(公告)号：US11881468B2

公开(公告)日：2024-01-23

申请号：US17456066

申请日：2021-11-22

Applicant: Micron Technology, Inc.

Inventor： Eiichi Nakano ,  Mark E. Tuttle

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/29 ,  H01L24/27 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/279 ,  H01L2224/2919 ,  H01L2224/29076 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/83851

Abstract: An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.