公开(公告)号：US10319724B2

公开(公告)日：2019-06-11

申请号：US16033377

申请日：2018-07-12

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Kris K. Brown ,  Raghunath Singanamalla ,  Vinay Nair ,  Fawad Ahmed ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  H01L29/78 ,  H01L27/02 ,  H01L27/06 ,  H01L49/02 ,  H01L29/10 ,  H01L29/94 ,  H01L23/528 ,  H01L29/08

Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.

公开(公告)号：US09391206B2

公开(公告)日：2016-07-12

申请号：US14992966

申请日：2016-01-11

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L21/00 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

公开(公告)号：US20190326292A1

公开(公告)日：2019-10-24

申请号：US16459956

申请日：2019-07-02

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C11/405 ,  G11C5/06

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20180301454A1

公开(公告)日：2018-10-18

申请号：US16006301

申请日：2018-06-12

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum SImsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/405 ,  G11C11/401

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US10079235B2

公开(公告)日：2018-09-18

申请号：US15664183

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06 ,  G11C11/401

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US20180061836A1

公开(公告)日：2018-03-01

申请号：US15664183

申请日：2017-07-31

Applicant: Micron Technology, Inc.

Inventor： Suraj J. Mathew ,  Raghunath Singanamalla ,  Fawad Ahmed ,  Kris K. Brown ,  Vinay Nair ,  Gloria Yang ,  Fatma Arzum Simsek-Ege ,  Diem Thy N. Tran

IPC: H01L27/108 ,  G11C5/06

CPC classification number: H01L27/108 ,  G11C5/063 ,  G11C11/401 ,  G11C11/405 ,  H01L27/10841 ,  H01L27/10864

Abstract: Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.

公开(公告)号：US09263341B2

公开(公告)日：2016-02-16

申请号：US14836257

申请日：2015-08-26

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

公开(公告)号：US20150279694A1

公开(公告)日：2015-10-01

申请号：US14740072

申请日：2015-06-15

Applicant: Micron Technology, Inc.

Inventor： Shivani Srivastava ,  Kunal Shrotri ,  Fawad Ahmed

IPC: H01L21/324 ,  H01L29/423 ,  H01L29/66 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L21/324 ,  H01L21/02164 ,  H01L21/02318 ,  H01L21/28185 ,  H01L21/28211 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

Abstract: Some embodiments include methods of forming silicon dioxide in which silicon dioxide is formed across silicon utilizing a first treatment temperature of no greater than about 1000° C., and in which an interface between the silicon dioxide and the silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. Some embodiments include methods of forming transistors in which a trench is formed to extend into monocrystalline silicon. Silicon dioxide is formed along multiple crystallographic planes along an interior of the trench utilizing a first treatment temperature of no greater than about 1000° C., and an interface between the silicon dioxide and the monocrystalline silicon is annealed utilizing a second treatment temperature which is at least about 1050° C. A transistor gate is formed within the trench, and a pair of source/drain regions is formed within the monocrystalline silicon adjacent the transistor gate. Some embodiments include DRAM cells.

Abstract translation: 一些实施方案包括形成二氧化硅的方法，其中使用不大于约1000℃的第一处理温度在硅上形成二氧化硅，并且其中二氧化硅和硅之间的界面利用第二处理温度 其为至少约1050℃。一些实施方案包括形成晶体管的方法，其中形成沟槽以延伸至单晶硅。 利用第一处理温度不大于约1000℃，沿着沟槽内部的多个结晶平面形成二氧化硅，并且利用第二处理温度对二氧化硅和单晶硅之间的界面进行退火 至少约1050℃。晶体管栅极形成在沟槽内，并且在与晶体管栅极相邻的单晶硅内形成一对源/漏区。 一些实施例包括DRAM单元。