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    Input/output capacitance measurement, and related methods, devices, and systems
    11.
    发明授权
    Input/output capacitance measurement, and related methods, devices, and systems 有权

    公开(公告)号：US11302387B2

    公开(公告)日：2022-04-12

    申请号：US16927535

    申请日：2020-07-13

    Applicant: Micron Technology, Inc.

    Inventor： Hyunui Lee

    IPC: H03K19/0185 ,  H03K3/00 ,  H03K3/356 ,  G11C11/4096 ,  H03K5/24 ,  G01R27/26 ,  G11C11/4076 ,  H03K3/037

    Abstract: A device may include a current source configured to couple a charged node to a ground voltage to generate a current. The device may include a second circuit coupled to the node and configured to compare, beginning during a first clock cycle of a clock signal and for each clock cycle of a number of clock cycles of the clock signal, the voltage at the node to a reference voltage to generate a result. The device may further include a control unit configured to: detect, upon completion of a subsequent clock cycle of the clock signal, a change in the result; determine, in response to the change in the result, a transition time based on a number of elapsed clock cycles from the first clock cycle to completion of the subsequent clock cycle; and determine a capacitance of the node based on the transition time. Related systems and methods are also described.

    INPUT/OUTPUT CAPACITANCE MEASUREMENT, AND RELATED METHODS, DEVICES, AND SYSTEMS
    12.
    发明申请
    INPUT/OUTPUT CAPACITANCE MEASUREMENT, AND RELATED METHODS, DEVICES, AND SYSTEMS 有权

    公开(公告)号：US20220013164A1

    公开(公告)日：2022-01-13

    申请号：US16927535

    申请日：2020-07-13

    Applicant: Micron Technology, Inc.

    Inventor： Hyunui Lee

    IPC: G11C11/4096 ,  H03K5/24 ,  H03K3/037 ,  G11C11/4076 ,  G01R27/26

    Abstract: A device may include a current source configured to couple a charged node to a ground voltage to generate a current. The device may include a second circuit coupled to the node and configured to compare, beginning during a first clock cycle of a clock signal and for each clock cycle of a number of clock cycles of the clock signal, the voltage at the node to a reference voltage to generate a result. The device may further include a control unit configured to: detect, upon completion of a subsequent clock cycle of the clock signal, a change in the result; determine, in response to the change in the result, a transition time based on a number of elapsed clock cycles from the first clock cycle to completion of the subsequent clock cycle; and determine a capacitance of the node based on the transition time. Related systems and methods are also described.

    Output impedance calibration, and related devices, systems, and methods
    13.
    发明授权
    Output impedance calibration, and related devices, systems, and methods 有权

    公开(公告)号：US11960906B2

    公开(公告)日：2024-04-16

    申请号：US18048588

    申请日：2022-10-21

    Applicant: Micron Technology, Inc.

    Inventor： Hyunui Lee

    IPC: G06F9/445 ,  G06F3/06 ,  G06F13/20 ,  G11C7/10 ,  G11C11/4093 ,  G06F1/10

    CPC classification number: G06F9/44505 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/20 ,  G11C7/1048 ,  G11C11/4093 ,  G06F1/10

    Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.

    Reference-voltage-generators within integrated assemblies
    15.
    发明授权
    Reference-voltage-generators within integrated assemblies 有权

    公开(公告)号：US11443788B1

    公开(公告)日：2022-09-13

    申请号：US17204063

    申请日：2021-03-17

    Applicant: Micron Technology, Inc.

    Inventor： Takamasa Suzuki ,  Yasuo Satoh ,  Yuan He ,  Hyunui Lee

    IPC: G11C5/14 ,  G11C8/08 ,  G11C7/06

    Abstract: Some embodiments include an integrated assembly having a memory region with memory cells and sense/access lines configured for addressing the memory cells, and having a reference-voltage-generator proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the sense/access lines. Some embodiments include an integrated assembly having a memory region with memory cells, digit lines and wordlines. Each of the memory cells is uniquely addressed with one of the wordlines in combination with one of the digit lines. The wordlines are coupled with driver circuitry and the digit lines are coupled with sensing circuitry. A reference-voltage-generator is proximate to the memory region. The reference-voltage-generator includes resistive units configured substantially identically to the wordlines and/or includes resistive units configured substantially identically to the digit lines.

    INTEGRATED ASSEMBLIES HAVING MEMORY CELLS WITH CAPACITIVE UNITS AND REFERENCE-VOLTAGE-GENERATORS WITH RESISTIVE UNITS
    16.
    发明申请
    INTEGRATED ASSEMBLIES HAVING MEMORY CELLS WITH CAPACITIVE UNITS AND REFERENCE-VOLTAGE-GENERATORS WITH RESISTIVE UNITS 有权

    公开(公告)号：US20220223191A1

    公开(公告)日：2022-07-14

    申请号：US17144461

    申请日：2021-01-08

    Applicant: Micron Technology, Inc.

    Inventor： Hyunui Lee ,  Takamasa Suzuki ,  Yasuo Satoh ,  Yuan He

    IPC: G11C11/4074

    Abstract: Embodiments include an integrated assembly having a deck over a base, and having memory cells supported by the deck. Each of the memory cells includes a capacitive unit and a transistor. The individual capacitive units of the memory cells each have a storage node electrode, a plate electrode, and a capacitor dielectric material between the storage node electrode and the plate electrode. A reference-voltage-generator includes resistive units supported by the deck. The resistive units are similar to the memory cells but include interconnecting units in place of the capacitive units. The interconnecting units of some adjacent resistive units are shorted to one another.

    OUTPUT IMPEDANCE CALIBRATION, AND RELATED DEVICES, SYSTEMS, AND METHODS
    17.
    发明申请
    OUTPUT IMPEDANCE CALIBRATION, AND RELATED DEVICES, SYSTEMS, AND METHODS 有权

    公开(公告)号：US20220214890A1

    公开(公告)日：2022-07-07

    申请号：US17141031

    申请日：2021-01-04

    Applicant: Micron Technology, Inc.

    Inventor： Hyunui Lee

    IPC: G06F9/445 ,  G11C11/4093 ,  G11C7/10 ,  G06F13/20 ,  G06F3/06

    Abstract: A device may include a number of drivers, wherein each driver of the number of drivers includes a number of transistors coupled to an output node. The device may further include circuitry coupled to the number of drivers. The circuitry may configure at least one driver of the number of drivers in each of a number of configurations, wherein each configuration of the number of configurations is associated with a calibration code of a number of calibration codes. Each configuration generates, in response to signal transmission via the output node, an associated channel performance response of a number of channel performance responses. The circuitry may also store a calibration code for the at least one unit driver, wherein the calibration code generates a desired channel performance response of the number of channel performance responses. Systems and related methods of operation are also described.

    IMPEDANCE CALIBRATION VIA A NUMBER OF CALIBRATION CIRCUITS, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS
    18.
    发明申请
    IMPEDANCE CALIBRATION VIA A NUMBER OF CALIBRATION CIRCUITS, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS 有权

    公开(公告)号：US20210319840A1

    公开(公告)日：2021-10-14

    申请号：US16848093

    申请日：2020-04-14

    Applicant: Micron Technology, Inc.

    Inventor： Hyunui Lee

    IPC: G11C29/12 ,  G11C29/02 ,  G11C7/10

    Abstract: Semiconductor devices are disclosed. A semiconductor device may include an input/output (I/O) interface area. The semiconductor device may also include a number of ZQ calibration circuits, wherein each of the number of ZQ calibration circuits is positioned adjacent to an associated portion of the I/O interface area. The semiconductor device may also include a number of interpolation circuits, wherein each of the number of interpolation circuits positioned adjacent to an associated portion of the I/O interface area and configured to generate a calibration code based on a number of other calibration codes. Further, portions of the I/O interface area associated with the number of interpolation circuits are at least partially positioned between portions of the I/O interface area associated with the number of ZQ calibration circuits. Methods and systems are also disclosed.

    Output drivers, and related methods, memory devices, and systems
    19.
    发明授权
    Output drivers, and related methods, memory devices, and systems 有权

    公开(公告)号：US10902907B1

    公开(公告)日：2021-01-26

    申请号：US16590668

    申请日：2019-10-02

    Applicant: Micron Technology, Inc.

    Inventor： Hyunui Lee

    IPC: G11C7/00 ,  G11C11/4096 ,  G11C11/4093 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

    Abstract: An output driver is disclosed. An output driver may include a pre-driver and a main driver coupled to the pre-driver. The main driver may include at least one switch, and a first transistor coupled between a first supply voltage and the at least one switch. The main driver may also include a second transistor coupled between a second, different supply voltage and the at least one switch. The at least one switch is configured to couple an output node of the output driver to one of the first transistor and the second transistor in response to receipt of a control signal. The main driver may also include a third transistor coupled between a reference voltage and the output node. An electronic system including at least one output driver, and methods of operating an output driver are also described.

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