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    Apparatuses and methods for compute components formed over an array of memory cells
    11.
    发明授权
    Apparatuses and methods for compute components formed over an array of memory cells 有权

    公开(公告)号：US10373666B2

    公开(公告)日：2019-08-06

    申请号：US15806123

    申请日：2017-11-07

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny

    IPC: G11C11/402 ,  G11C11/406 ,  G11C11/403 ,  G11C5/02 ,  G11C7/10 ,  G11C11/407

    Abstract: The present disclosure includes apparatuses and methods related to compute components formed over an array of storage elements. An example apparatus comprises a base substrate material and an array of memory cells formed over the base substrate material. The array can include a plurality of access transistors comprising a first semiconductor material. A compute component can be formed over and coupled to the array. The compute component can include a plurality of compute transistors comprising a second semiconductor material. The second semiconductor material can have a higher concentration of doping ions than the first semiconductor material.

    DATA TRANSFER BETWEEN SUBARRAYS IN MEMORY
    12.
    发明申请
    DATA TRANSFER BETWEEN SUBARRAYS IN MEMORY 审中-公开

    公开(公告)号：US20180357007A1

    公开(公告)日：2018-12-13

    申请号：US15616642

    申请日：2017-06-07

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Glen E. Hush ,  Richard C. Murphy

    IPC: G06F3/06 ,  G11C11/4091

    CPC classification number: G11C7/06 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0673 ,  G11C11/4091

    Abstract: The present disclosure includes apparatuses and methods for data transfer between subarrays in memory. An example may include a first subarray of memory cells and a second subarray of memory cells, wherein a first portion of memory cells of the first subarray and a first portion of memory cells of the second subarray are coupled to a first sensing circuitry stripe. A third subarray of memory cells can include a first portion of memory cells coupled to a second sensing circuitry stripe. A second portion of memory cells of the second subarray and a second portion of memory cells of the third subarray can be coupled to a third sensing circuitry stripe. A particular row of the second array can include memory cells from the first portion of memory cells in the second array coupled to memory cells from the second portion of memory cells in the second array.

    APPARATUSES AND METHODS TO REVERSE DATA STORED IN MEMORY
    15.
    发明申请
    APPARATUSES AND METHODS TO REVERSE DATA STORED IN MEMORY 有权
    反映存储器中存储的数据的装置和方法

    公开(公告)号：US20160306584A1

    公开(公告)日：2016-10-20

    申请号：US15098707

    申请日：2016-04-14

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Glen E. Hush

    IPC: G06F3/06

    CPC classification number: G11C11/4091 ,  G11C7/1006 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  G11C16/28 ,  G11C2211/4013

    Abstract: Apparatuses and methods are provided for reversing data stored in memory. An example apparatus comprises an array of memory cells, a first plurality of sensing components corresponding to a respective first plurality of columns of the array, a second plurality of sensing components corresponding to a respective second plurality of columns of the array, and a plurality of shared input/output (I/O) lines (which may be referred to as SIO lines). Each one of the plurality of SIO lines can be selectively coupled to a respective subset of the first plurality of sensing components and to a respective subset of the second plurality of sensing components. The apparatus can include a controller configured to control reversing a logical sequence of data stored in a group of memory cells coupled to a first access line of the array by performing a plurality of transfer operations via the plurality of SIO lines.

    Abstract translation: 提供了用于反转存储在存储器中的数据的装置和方法。 示例性设备包括存储器单元阵列，对应于阵列的相应第一多个列的第一多个感测组件，对应于阵列的相应第二多个列的第二多个感测组件，以及多个 共享输入/输出（I / O）线（可以称为SIO线）。 多个SIO线中的每一个可以选择性地耦合到第一多个感测部件的相应子集以及第二多个感测部件的相应子集。 该装置可以包括控制器，其被配置为通过经由多个SIO线执行多个传送操作来控制存储在耦合到阵列的第一接入线的一组存储器单元中的数据的逻辑序列。

    Data transfer between subarrays in memory
    18.
    发明授权
    Data transfer between subarrays in memory 有权

    公开(公告)号：US10510381B2

    公开(公告)日：2019-12-17

    申请号：US16138287

    申请日：2018-09-21

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Glen E. Hush ,  Richard C. Murphy

    IPC: G11C7/06 ,  G06F3/06 ,  G11C11/4091 ,  G11C7/10 ,  G11C5/02

    Abstract: The present disclosure includes apparatuses and methods for data transfer between subarrays in memory. An example may include a first subarray of memory cells and a second subarray of memory cells, wherein a first portion of memory cells of the first subarray and a first portion of memory cells of the second subarray are coupled to a first sensing circuitry stripe. A third subarray of memory cells can include a first portion of memory cells coupled to a second sensing circuitry stripe. A second portion of memory cells of the second subarray and a second portion of memory cells of the third subarray can be coupled to a third sensing circuitry stripe. A particular row of the second array can include memory cells from the first portion of memory cells in the second array coupled to memory cells from the second portion of memory cells in the second array.

    APPARATUSES AND METHODS FOR PARALLEL WRITING TO MULTIPLE MEMORY DEVICE STRUCTURES
    19.
    发明申请
    APPARATUSES AND METHODS FOR PARALLEL WRITING TO MULTIPLE MEMORY DEVICE STRUCTURES 审中-公开

    公开(公告)号：US20190286337A1

    公开(公告)日：2019-09-19

    申请号：US16433803

    申请日：2019-06-06

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Glen E. Hush ,  Troy A. Manning ,  Timothy P. Finkbeiner

    IPC: G06F3/06 ,  G11C7/10 ,  G06F15/78 ,  G11C29/28 ,  G11C8/12

    Abstract: The present disclosure includes apparatuses and methods related to a memory device as the store to pre-resolved instructions. An example apparatus comprises a memory device coupled to a host via a data bus and a control bus. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes sense amplifiers and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of address translated instructions and/or constant data from the host. The memory controller is configured to write the address translated instructions and/or constant data to a plurality of locations in a bank of the memory device in parallel.

    APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY
    20.
    发明申请
    APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY 审中-公开

    公开(公告)号：US20190108863A1

    公开(公告)日：2019-04-11

    申请号：US16215122

    申请日：2018-12-10

    Applicant: Micron Technology, Inc.

    Inventor： Jason T. Zawodny ,  Sanjay Tiwari

    IPC: G11C7/06 ,  G11C15/04 ,  G11C8/10 ,  G11C8/16

    CPC classification number: G11C7/065 ,  G11C8/10 ,  G11C8/16 ,  G11C15/043

    Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and one of the plurality of sense lines. The access line can be a same access line as one of the plurality of access lines. The example apparatus comprises a controller configured to cause a corner turn operation on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells to be performed using sensing circuitry.

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