Error Logging for a Memory Device with On-Die Wear Leveling

    公开(公告)号:US20230350574A1

    公开(公告)日:2023-11-02

    申请号:US17731100

    申请日:2022-04-27

    CPC classification number: G06F3/0619 G06F3/0653 G06F3/0679 G06F3/0676

    Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

    MULTIPLE CONCURRENT MODULATION SCHEMES IN A MEMORY SYSTEM

    公开(公告)号:US20200020367A1

    公开(公告)日:2020-01-16

    申请号:US16530525

    申请日:2019-08-02

    Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

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