公开(公告)号：US20230350574A1

公开(公告)日：2023-11-02

申请号：US17731100

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Bryan David Kerstetter ,  Donald M. Morgan ,  Alan J. Wilson ,  John David Porter ,  Jeffrey P. Wright

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F3/0676

Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

公开(公告)号：US11775460B2

公开(公告)日：2023-10-03

申请号：US17864023

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093 ,  G11C7/10 ,  G11C11/4096 ,  G11C5/04

CPC classification number: G06F13/1689 ,  G06F13/4068 ,  G06F13/42 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1069 ,  G11C11/4093 ,  G11C11/4096

Abstract: Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

公开(公告)号：US10832748B2

公开(公告)日：2020-11-10

申请号：US16666045

申请日：2019-10-28

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C8/12 ,  G06F12/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/4093

Abstract: Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer.

公开(公告)号：US10811372B2

公开(公告)日：2020-10-20

申请号：US16416210

申请日：2019-05-18

Applicant: Micron Technology, Inc.

Inventor： James E. Davis ,  Kevin G. Duesman ,  Jeffrey P. Wright ,  Warren L. Boyer

IPC: H01L23/60 ,  H01L23/00 ,  H01L23/538 ,  H01L25/04 ,  G11C5/02 ,  H01L25/065

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.

公开(公告)号：US20200212032A1

公开(公告)日：2020-07-02

申请号：US16234208

申请日：2018-12-27

Applicant: Micron Technology, Inc.

Inventor： Kevin G. Duesman ,  James E. Davis ,  Warren L. Boyer ,  Jeffrey P. Wright

IPC: H01L27/02 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first contact pad, and the substrate is electrically isolated from the second contact pad.

公开(公告)号：US20200020367A1

公开(公告)日：2020-01-16

申请号：US16530525

申请日：2019-08-02

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: G11C7/10 ,  G11C11/22 ,  G06F1/3234 ,  G06F13/42

Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

公开(公告)号：US20190273642A1

公开(公告)日：2019-09-05

申请号：US16419870

申请日：2019-05-22

Applicant: Micron Technology, Inc.

Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

IPC: H04L27/04 ,  G11C8/12 ,  G06F13/38 ,  G11C5/06 ,  G06F12/02 ,  H04L27/06 ,  H04L27/02 ,  H04L25/49 ,  G11C7/10 ,  G06F13/16

Abstract: Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

公开(公告)号：US10403585B2

公开(公告)日：2019-09-03

申请号：US16138003

申请日：2018-09-21

Applicant: Micron Technology, Inc.

Inventor： James E. Davis ,  Kevin G. Duesman ,  Jeffrey P. Wright ,  Warren L. Boyer

IPC: H01L23/60 ,  H01L23/538 ,  H01L25/04 ,  H01L23/00 ,  G11C5/02 ,  H01L25/065

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements, and a plated pad electrically coupling at least a part of the first contact pad to at least a part of the second contact pad. The substrate includes a substrate contact electrically coupled to the plated pad on the die.

公开(公告)号：US10147472B2

公开(公告)日：2018-12-04

申请号：US15656084

申请日：2017-07-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William F. Jones ,  Jeffrey P. Wright

IPC: G11C7/00 ,  G11C8/10 ,  G11C11/406 ,  G11C11/408 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

Abstract: Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

公开(公告)号：US20180315466A1

公开(公告)日：2018-11-01

申请号：US15583023

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： Scott J. Derner ,  Huy T. Vo ,  Patrick Mullarkey ,  Jeffrey P. Wright ,  Michael A. Shore

IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/40615 ,  G11C11/4072 ,  G11C11/4094 ,  G11C11/4096

Abstract: Systems and methods are provided for implementing an array rest mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.