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公开(公告)号：US20220254644A1
公开(公告)日：2022-08-11
申请号：US17730478
申请日：2022-04-27
Applicant: Micron Technology, Inc.
Inventor： Baosuo Zhou , Mirzafer K. Abatchev , Ardavan Niroomand , Paul A. Morgan , Shuang Meng , Joseph Neil Greeley , Brian J. Coppa
IPC: H01L21/306 , H01L21/033 , H01L21/308 , H01L23/00
Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
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公开(公告)号：US10727242B2
公开(公告)日：2020-07-28
申请号：US16372563
申请日：2019-04-02
Applicant: Micron Technology, Inc.
Inventor： Justin B. Dorhout , Kunal R. Parekh , Matthew Park , Joseph Neil Greeley , Chet E. Carter , Martin C. Roberts , Indra V. Chary , Vinayak Shamanna , Ryan Meyer , Paolo Tessariol
IPC: H01L27/11 , H01L27/11556 , H01L27/11573 , H01L27/11519 , H01L27/11565 , H01L27/11582
Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.
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公开(公告)号：US10137481B2
公开(公告)日：2018-11-27
申请号：US14605218
申请日：2015-01-26
Applicant: Micron Technology, Inc.
Inventor： Joseph Neil Greeley , Dan Millward , Wayne Huang
Abstract: Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.
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公开(公告)号：US10014309B2
公开(公告)日：2018-07-03
申请号：US15231950
申请日：2016-08-09
Applicant: Micron Technology, Inc.
Inventor： Justin B. Dorhout , Kunal R. Parekh , Matthew Park , Joseph Neil Greeley , Chet E. Carter , Martin C. Roberts , Indra V. Chary , Vinayak Shamanna , Ryan Meyer , Paolo Tessariol
IPC: H01L21/336 , H01L27/11556 , H01L27/11519 , H01L27/11582 , H01L27/11565
CPC classification number: H01L27/11556 , H01L27/11519 , H01L27/11565 , H01L27/11573 , H01L27/11582
Abstract: An array of elevationally-extending strings of memory cells, where the memory cells individually comprise a programmable charge storage transistor, comprises a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region. The first region comprises vertically-alternating tiers of insulative material and control gate material. The second region comprises vertically-alternating tiers of different composition insulating materials laterally of the first region. A channel pillar comprising semiconductive channel material extends elevationally through multiple of the vertically-alternating tiers within the first region. Tunnel insulator, programmable charge storage material, and control gate blocking insulator are between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region. Conductive vias extend elevationally through the vertically-alternating tiers in the second region. An elevationally-extending wall is laterally between the first and second regions. The wall comprises the programmable charge storage material and the semiconductive channel material. Other embodiments and aspects, including method, are disclosed.
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公开(公告)号：US20170372913A1
公开(公告)日：2017-12-28
申请号：US15681066
申请日：2017-08-18
Applicant: Micron Technology, Inc.
Inventor： Baosuo Zhou , Mirzafer K. Abatchev , Ardavan Niroomand , Paul A. Morgan , Shuang Meng , Joseph Neil Greeley , Brian J. Coppa
IPC: H01L21/306 , H01L23/00 , H01L21/033 , H01L21/308
CPC classification number: H01L21/30625 , H01L21/0335 , H01L21/0337 , H01L21/0338 , H01L21/30604 , H01L21/3086 , H01L21/3088 , H01L23/564 , H01L2924/0002 , H01L2924/00
Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
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Patent Agency Ranking
公开(公告)号：US09666801B2
公开(公告)日：2017-05-30
申请号：US15156105
申请日：2016-05-16
Applicant: Micron Technology, Inc.
Inventor： Nishant Sinha , John Smythe , Bhaskar Srinivasan , Gurtej S. Sandhu , Joseph Neil Greeley , Kunal R. Parekh
CPC classification number: H01L45/1683 , H01L27/2472 , H01L45/04 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/146 , H01L45/147 , H01L45/16
Abstract: A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Metal oxide-comprising material is formed over the first conductive electrode. Etch stop material is deposited over the metal oxide-comprising material. Conductive material is deposited over the etch stop material. A second conductive electrode of the memory cell which comprises the conductive material received is formed over the etch stop material. Such includes etching through the conductive material to stop relative to the etch stop material and forming the non-volatile resistive oxide memory cell to comprise the first and second conductive electrodes having both the metal oxide-comprising material and the etch stop material therebetween. Other implementations are contemplated.
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公开(公告)号：US20150126016A1
公开(公告)日：2015-05-07
申请号：US14596429
申请日：2015-01-14
Applicant: Micron Technology, Inc.
Inventor： Joseph Neil Greeley , Prashant Raghu , Niraj B. Rana
IPC: H01L49/02 , H01L21/3213 , H01L27/108
CPC classification number: H01L28/92 , H01L21/32133 , H01L27/108 , H01L27/10852 , H01L27/10861 , H01L28/90
Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.
Abstract translation: 形成电容器的方法包括在衬底上形成支撑材料。 第一电容器电极形成在支撑材料中的单个开口内。 使用液体蚀刻流体仅部分地将第一蚀刻部分地进入支撑材料，以暴露第一电容器电极的各个侧壁的正面外侧部分。 使用干蚀刻流体将第二蚀刻进入支撑材料，以暴露各个第一电容器电极的侧壁的正面内部。 在第一电容器电极的侧壁的外部和内部上形成电容器电介质。 在电容器电介质上形成第二电容电极。
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公开(公告)号：US11139159B2
公开(公告)日：2021-10-05
申请号：US16165296
申请日：2018-10-19
Applicant: Micron Technology, Inc.
Inventor： Joseph Neil Greeley , Dan Millward , Wayne Huang
Abstract: Some embodiments include methods of removing particles from over surfaces of semiconductor substrates. Liquid may be flowed across the surfaces and the particles. While the liquid is flowing, electrophoresis and/or electroosmosis may be utilized to enhance transport of the particles from the surfaces and into the liquid. In some embodiments, temperature, pH and/or ionic strength within the liquid may be altered to assist in the removal of the particles from over the surfaces of the substrates.
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公开(公告)号：US10607844B2
公开(公告)日：2020-03-31
申请号：US15993568
申请日：2018-05-30
Applicant: Micron Technology, Inc.
Inventor： Baosuo Zhou , Mirzafer K. Abatchev , Ardavan Niroomand , Paul A. Morgan , Shuang Meng , Joseph Neil Greeley , Brian J. Coppa
IPC: H01L21/306 , H01L21/033 , H01L21/308 , H01L23/00
Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.
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公开(公告)号：US20190206884A1
公开(公告)日：2019-07-04
申请号：US15903254
申请日：2018-02-23
Applicant: Micron Technology, Inc
Inventor： Wei Yeeng Ng , Ian Laboriante , Joseph Neil Greeley , Tom J. John , Ho Yee Hui
IPC: H01L27/11556 , H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L21/28 , H01L21/3213 , H01L21/311 , H01L21/768 , H01L23/522
Abstract: A method of forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising alternating insulative tiers and wordline tiers. A select gate tier is above an upper of the insulative tiers. Channel openings extend through the alternating tiers and the select gate tier. Charge-storage material is formed within the channel openings elevationally along the alternating tiers and the select gate tier. Sacrificial material is formed within the channel openings laterally over the charge-storage material that is laterally over the select gate tier and that is laterally over the alternating tiers. Elevationally-outer portions of each of the charge-storage material and the sacrificial material that are within the channel openings are etched. After such etching, the sacrificial material is removed from the channel openings. After such removing, insulative charge-passage material then channel material are formed within the channel openings laterally over the charge-storage material that is laterally over the wordline tiers. The wordline tiers are formed to comprise control-gate material having terminal ends corresponding to control-gate regions of individual memory cells and to have a charge-blocking region of the individual memory cells laterally between the charge-storage material and individual of the control-gate regions.
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