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    Memory Systems and Memory Programming Methods
    11.
    发明申请
    Memory Systems and Memory Programming Methods 审中-公开

    公开(公告)号：US20190139606A1

    公开(公告)日：2019-05-09

    申请号：US16235497

    申请日：2018-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Makoto Kitagawa ,  Adam Johnson

    IPC: G11C13/00

    Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline.

    Memory cell verification circuits, memory cell sense circuits and memory cell verification methods
    12.
    发明授权
    Memory cell verification circuits, memory cell sense circuits and memory cell verification methods 有权

    公开(公告)号：US09799398B2

    公开(公告)日：2017-10-24

    申请号：US15096135

    申请日：2016-04-11

    Applicant: Micron Technology, Inc.

    Inventor： Makoto Kitagawa ,  Kerry Tedrow

    IPC: G11C7/02 ,  G11C13/00 ,  G11C7/06 ,  G11C11/56

    CPC classification number: G11C13/0064 ,  G11C7/062 ,  G11C11/5614 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/79

    Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.

    Memory devices, memory device operational methods, and memory device implementation methods
    15.
    发明授权
    Memory devices, memory device operational methods, and memory device implementation methods 有权
    存储器件，存储器件操作方法和存储器件实现方法

    公开(公告)号：US09230616B2

    公开(公告)日：2016-01-05

    申请号：US14151704

    申请日：2014-01-09

    Applicant: Micron Technology, Inc.

    Inventor： Yogesh Luthra ,  Makoto Kitagawa

    IPC: G11C7/04 ,  G01K13/00 ,  G11C11/406

    CPC classification number: G11C7/04 ,  G01K1/02 ,  G01K13/00 ,  G01K2219/00 ,  G11C11/40626 ,  G11C13/0002 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/3418

    Abstract: Memory devices, memory device operational methods, and memory device implementation methods are described. According to one arrangement, a memory device includes memory circuitry configured to store data in a plurality of different data states, temperature sensor circuitry configured to sense a temperature of the memory device and to generate an initial temperature output which is indicative of the temperature of the memory device, and conversion circuitry coupled with the temperature sensor circuitry and configured to convert the initial temperature output into a converted temperature output which is indicative of the temperature of the memory device at a selected one of a plurality of possible different temperature resolutions, and wherein the converted temperature output is utilized by the memory circuitry to implement at least one operation with respect to storage of the data.

    Abstract translation: 描述了存储器件，存储器件操作方法和存储器件实现方法。 根据一种布置，存储器件包括被配置为存储多个不同数据状态的数据的存储器电路，温度传感器电路被配置为感测存储器件的温度并产生初始温度输出，其表示温度 存储器件和转换电路，其与温度传感器电路耦合并且被配置为将初始温度输出转换成转换后的温度输出，该转换温度输出指示存储器件在多个可能的不同温度分辨率中选定的一个温度， 转换的温度输出由存储器电路用于实现关于数据存储的至少一个操作。

    Memory Systems and Memory Programming Methods
    16.
    发明申请
    Memory Systems and Memory Programming Methods 审中-公开
    内存系统和内存编程方法

    公开(公告)号：US20150179256A1

    公开(公告)日：2015-06-25

    申请号：US14137586

    申请日：2013-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Makoto Kitagawa ,  Adam Johnson

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C11/1655 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C13/0033 ,  G11C2213/79

    Abstract: Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a plurality of memory cells individually configured to have a plurality of different memory states, a plurality of bitlines coupled with the memory cells, access circuitry coupled with the bitlines and configured to apply a plurality of program signals to the bitlines to program the memory cells between the different memory states, a controller configured to control the access circuitry to provide a first program signal and a second program signal to one of the bitlines coupled with one of the memory cells to program the one memory cell from a first of the memory states to a second of the memory states, wherein the second program signal has an increased electrical characteristic compared with the first program signal, and selection circuitry configure to couple another of the bitlines which is immediately adjacent to the one bitline to a node having a first voltage which is different than a second voltage of the one bitline during the provision of the first and second program signals to the one bitline.

    Abstract translation: 描述了存储器系统和存储器编程方法。 根据一种布置，存储器系统包括单独配置为具有多个不同存储器状态的多个存储器单元，与存储器单元耦合的多个位线，与位线耦合的存取电路，并被配置为施加多个程序信号 到位线以对不同存储器状态之间的存储器单元进行编程，控制器被配置为控制访问电路以向与存储器单元之一耦合的位线之一提供第一编程信号和第二编程信号，以对一个存储器 从所述存储器状态的第一存储器状态到所述存储器状态的第二存储器状态，其中所述第二编程信号与所述第一编程信号相比具有增加的电特性，并且所述选择电路被配置为耦合与所述存储器状态紧邻的另一位线 位于具有与一个位线的第二电压不同的第一电压的节点 将第一和第二程序信号提供给一个位线。

    WORD LINE VOLTAGE CONTROL FOR REDUCED VOLTAGE DISTURBANCE DURING MEMORY OPERATIONS
    18.
    发明公开
    WORD LINE VOLTAGE CONTROL FOR REDUCED VOLTAGE DISTURBANCE DURING MEMORY OPERATIONS 审中-公开

    公开(公告)号：US20240212735A1

    公开(公告)日：2024-06-27

    申请号：US18524708

    申请日：2023-11-30

    Applicant: Micron Technology, Inc.

    Inventor： Makoto Kitagawa

    IPC: G11C11/22

    CPC classification number: G11C11/2257 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2273 ,  G11C11/2275

    Abstract: A memory cell may include a capacitor and a switch. Accessing the memory cell in a memory array of a memory device may include applying a word line voltage to the switch to electrically couple the capacitor to a data line. However, if not compensated for, applying the word line voltage may induce undesired voltages on adjacent memory cells of the memory arrays. Systems and methods are described to reduce an effect of one or more parasitic capacitors causing the undesired voltage disturbance. For example, the memory array may provide compensatory voltages to adjacent word lines of a target word line to compensate for such undesired parasitic capacitors. Accordingly, an undesired voltage disturbance of the memory cells may be reduced.

    PLATE LINE DRIVERS WITH A SHARED BIAS DEVICE
    19.
    发明公开
    PLATE LINE DRIVERS WITH A SHARED BIAS DEVICE 审中-公开

    公开(公告)号：US20240212734A1

    公开(公告)日：2024-06-27

    申请号：US18518090

    申请日：2023-11-22

    Applicant: Micron Technology, Inc.

    Inventor： Makoto Kitagawa

    IPC: G11C11/22

    CPC classification number: G11C11/2255 ,  G11C11/221

    Abstract: A variety of applications can include apparatus having a memory device comprising plate select lines coupled to capacitors of memory cells of the memory device, plate line drivers coupled to the plate select lines, and a bias device coupled to each plate line driver. Use of a single bias device can allow for generation of robust current across multiple plate line drivers. The plate line drivers can be arranged with different formats that can operate with a single bias device. Plate select lines and the plate line driver can be structured in a scheme to balance the number of plate select lines and device counts for the plate line drivers.

    DISTRIBUTED MEMORY DATA PATH FOR CIRCUIT UNDER ARRAY
    20.
    发明公开
    DISTRIBUTED MEMORY DATA PATH FOR CIRCUIT UNDER ARRAY 审中-公开

    公开(公告)号：US20240211152A1

    公开(公告)日：2024-06-27

    申请号：US18524739

    申请日：2023-11-30

    Applicant: Micron Technology, Inc.

    Inventor： Makoto Kitagawa

    IPC: G06F3/06

    CPC classification number: G06F3/0635 ,  G06F3/0604 ,  G06F3/0679

    Abstract: A memory device may include various circuitry including multiple memory banks and a circuit under array. The circuit under array may include a number of control blocks each coupling to a respective memory bank. The control blocks may route data and commands to the memory cells of the memory arrays of the respective memory banks. In particular, the control blocks may include routing circuitry including column routing circuits, row routing circuits, and coupling routing circuits to route data between external devices and the memory banks. For example, the coupling routing circuits may couple the column routing circuits and the row routing circuits. Implementing the coupling routing circuits with the control blocks may reduce a footprint of the circuit under array.

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