公开(公告)号：US20240403165A1

公开(公告)日：2024-12-05

申请号：US18667799

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Nathan A. Eckel ,  James Brian Johnson ,  Paul A. Laberge

IPC: G06F11/10 ,  G06F11/14

Abstract: Methods, systems, and devices for information broadcast techniques for stacked memory architectures are described. A semiconductor system may include multiple instances of interface circuitry of a semiconductor die that are each operable for accessing a respective set of one or more memory arrays of one or more other semiconductor dies, as well as read-only storage for storing information that is common to the multiple instances of the interface circuitry. In some implementations, such read-only storage may include one-time programmable memory elements (e.g., fuses, antifuses) that are located in at least one of the one or more other semiconductor dies, and are accessible by each of the multiple instances of interface circuitry. The read-only storage may store information that supports common aspects of interface circuitry operations such as initialization operations, evaluation operations, configuration operations, access operations, or other operations, which may be broadcast to the multiple instances of interface circuitry.

公开(公告)号：US11650925B2

公开(公告)日：2023-05-16

申请号：US16717160

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Eric R. Fox ,  Nathan A. Eckel

IPC: G06F9/30 ,  G06F12/0868 ,  G06F12/06 ,  G06F9/4401 ,  G06F9/38 ,  G11C29/12 ,  G06F9/48 ,  G06F13/16 ,  G06F13/10

CPC classification number: G06F12/0868 ,  G06F9/30101 ,  G06F9/3869 ,  G06F9/4411 ,  G06F9/4806 ,  G06F12/0638 ,  G06F13/102 ,  G06F13/1689 ,  G11C29/12

Abstract: A method includes receiving a signal at a memory sub-system controller to perform an operation. The method can further include, in response to receiving the signal, enabling, by the memory sub-system controller, an interface to transfer data to or from a registering clock driver (RCD) component. The RCD component is coupled to the memory sub-system controller. The method can further include transferring the data to or from the RCD component via the interface. The method can further include, in response to the enablement of the interface being unsuccessful, transferring control of a memory device to the memory sub-system controller.

公开(公告)号：US11579979B2

公开(公告)日：2023-02-14

申请号：US17382889

申请日：2021-07-22

Applicant: Micron Technology, Inc.

Inventor： James E. Dunn ,  Nathan A. Eckel

IPC: G06F11/14 ,  G11C14/00 ,  G11C11/4072 ,  G06F13/42 ,  G11C5/14 ,  G11C7/20 ,  G11C11/406

Abstract: Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.

公开(公告)号：US11579791B2

公开(公告)日：2023-02-14

申请号：US17065226

申请日：2020-10-07

Applicant: Micron Technology, Inc.

Inventor： Jeffery J. Leyda ,  Nathan A. Eckel

IPC: G06F3/06 ,  G06F12/0804

Abstract: A variety of applications can include systems and/or methods of partial save of memory in an apparatus such as a non-volatile dual in-line memory module. In various embodiments, a set of control registers of a non-volatile dual in-line memory module can be configured to contain an identification of a portion of dynamic random-access memory of the non-volatile dual in-line memory module from which to back up content to non-volatile memory of the non-volatile dual in-line memory module. Registers of the set of control registers may also be allotted to contain an amount of content to transfer from the dynamic random-access memory content to the non-volatile memory. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20210210155A1

公开(公告)日：2021-07-08

申请号：US17211133

申请日：2021-03-24

Applicant: Micron Technology, Inc.

Inventor： Nathan A. Eckel ,  Keith A. Benjamin

IPC: G11C29/02 ,  G11C29/48 ,  G11C29/12 ,  G11C29/50 ,  G11C29/38

Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.

公开(公告)号：US20210182201A1

公开(公告)日：2021-06-17

申请号：US16717160

申请日：2019-12-17

Applicant: Micron Technology, Inc.

Inventor： Eric R. Fox ,  Nathan A. Eckel

IPC: G06F12/0868 ,  G06F12/06 ,  G06F9/4401 ,  G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F13/16 ,  G06F13/10 ,  G11C29/12

Abstract: A method includes receiving a signal at a memory sub-system controller to perform an operation. The method can further include, in response to receiving the signal, enabling, by the memory sub-system controller, an interface to transfer data to or from a registering clock driver (RCD) component. The RCD component is coupled to the memory sub-system controller. The method can further include transferring the data to or from the RCD component via the interface. The method can further include, in response to the enablement of the interface being unsuccessful, transferring control of a memory device to the memory sub-system controller.

公开(公告)号：US10984881B1

公开(公告)日：2021-04-20

申请号：US16713108

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Nathan A. Eckel ,  Keith A. Benjamin

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/38 ,  G11C29/50 ,  G11C29/12 ,  G11C29/48

Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.

公开(公告)号：US20250045389A1

公开(公告)日：2025-02-06

申请号：US18763983

申请日：2024-07-03

Applicant: Micron Technology, Inc.

Inventor： Chun-Yi Liu ,  Lance P. Johnson ,  Nathan A. Eckel ,  James Brian Johnson

IPC: G06F21/55

Abstract: Methods, systems, and devices for row hammer mitigation reliability in stacked memory architectures are described. A spare counter may be implemented at a first interface block of a logic die to enable increased reliability and efficiency in row hammer mitigation. The first interface block may use a spare counter in case of an error associated with a counter at a memory array die. A second interface block of an array die may identify an error associated with a counter of a memory array and may transmit an indication of the error to the first interface block. The first interface block may receive the indication and may activate a spare counter to track access operations on (e.g., activations of) the row based on the indication. The first interface block may use the spare counter to evaluate whether to transmit refresh signaling to the second interface block for row hammer mitigation.

公开(公告)号：US20250045388A1

公开(公告)日：2025-02-06

申请号：US18763963

申请日：2024-07-03

Applicant: Micron Technology, Inc.

Inventor： Nathan A. Eckel ,  Chun-Yi Liu ,  Lance P. Johnson ,  James Brian Johnson ,  Yang Lu

IPC: G06F21/55

Abstract: Methods, systems, and devices for row hammer mitigation for stacked memory architectures are described. A semiconductor system, such as a memory system, may distribute operations for row hammer mitigation across circuitry of the semiconductor system. A first interface block of a first die of the semiconductor system may exchange signaling with a second interface block of a second die of the semiconductor system to perform row hammer mitigation operations. The second die may implement counters to track quantities of access operations associated with respective rows of memory cells of the second die. The second interface block may transmit alert signaling to the first interface block based on a value of a counter, and the first interface block may evaluate the alert signaling and transmit refresh signaling to the second interface block to perform one or more refresh operations.

公开(公告)号：US20210349783A1

公开(公告)日：2021-11-11

申请号：US17382889

申请日：2021-07-22

Applicant: Micron Technology, Inc.

Inventor： James E. Dunn ,  Nathan A. Eckel

IPC: G06F11/14 ,  G11C14/00 ,  G06F13/42 ,  G11C5/14 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/406

Abstract: Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.