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    METHODS OF SELECTIVELY DOPING CHALCOGENIDE MATERIALS AND METHODS OF FORMING SEMICONDUCTOR DEVICES
    13.
    发明申请
    METHODS OF SELECTIVELY DOPING CHALCOGENIDE MATERIALS AND METHODS OF FORMING SEMICONDUCTOR DEVICES 有权
    选择性聚合材料的方法和形成半导体器件的方法

    公开(公告)号：US20150140777A1

    公开(公告)日：2015-05-21

    申请号：US14607329

    申请日：2015-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Jerome A. Imonigie ,  Prashant Raghu ,  Theodore M. Taylor ,  Scott E. Sills

    IPC: H01L45/00

    CPC classification number: H01L45/1658 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1641

    Abstract: Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material. A method of doping a chalcogenide material of a memory cell with at least one transition metal without using an etch or chemical mechanical planarization process to remove the transition metal from an insulative material of the memory cell is also disclosed, wherein the chalcogenide material is not silver selenide.

    Abstract translation: 选择性地形成金属掺杂的硫族化物材料的方法包括将硫族化物材料暴露于过渡金属溶液，并将过渡溶液的过渡金属掺入硫族化物材料中，而基本上不将过渡金属掺入相邻的材料中。 硫族化物材料不是硒化银。 另一种方法包括形成与绝缘材料相邻并与其接触的硫族化物材料，将硫族化物材料和绝缘材料暴露于过渡金属溶液，并将过渡金属溶液的过渡金属扩散到硫族化物材料中，同时基本上没有过渡金属扩散 进入绝缘材料。 还公开了一种使用至少一种过渡金属掺杂存储单元的硫族化物材料而不使用蚀刻或化学机械平坦化工艺以从存储器单元的绝缘材料除去过渡金属的方法，其中硫族化物材料不是银 硒化物

    Methods of Forming Capacitors
    18.
    发明申请
    Methods of Forming Capacitors 有权
    形成电容器的方法

    公开(公告)号：US20150126016A1

    公开(公告)日：2015-05-07

    申请号：US14596429

    申请日：2015-01-14

    Applicant: Micron Technology, Inc.

    Inventor： Joseph Neil Greeley ,  Prashant Raghu ,  Niraj B. Rana

    IPC: H01L49/02 ,  H01L21/3213 ,  H01L27/108

    CPC classification number: H01L28/92 ,  H01L21/32133 ,  H01L27/108 ,  H01L27/10852 ,  H01L27/10861 ,  H01L28/90

    Abstract: A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric.

    Abstract translation: 形成电容器的方法包括在衬底上形成支撑材料。 第一电容器电极形成在支撑材料中的单个开口内。 使用液体蚀刻流体仅部分地将第一蚀刻部分地进入支撑材料，以暴露第一电容器电极的各个侧壁的正面外侧部分。 使用干蚀刻流体将第二蚀刻进入支撑材料，以暴露各个第一电容器电极的侧壁的正面内部。 在第一电容器电极的侧壁的外部和内部上形成电容器电介质。 在电容器电介质上形成第二电容电极。

    Methods of treating semiconductor substrates, methods of forming openings during semiconductor fabrication, and methods of removing particles from over semiconductor substrates
    19.
    发明授权
    Methods of treating semiconductor substrates, methods of forming openings during semiconductor fabrication, and methods of removing particles from over semiconductor substrates 有权
    处理半导体衬底的方法，半导体制造期间形成开口的方法，以及从半导体衬底上去除颗粒的方法

    公开(公告)号：US08969217B2

    公开(公告)日：2015-03-03

    申请号：US13948043

    申请日：2013-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Janos Fucsko ,  Niraj B. Rana ,  Sandra Tagg ,  Robert J. Hanson ,  Gundu M. Sabde ,  Donald L. Yates ,  Patrick M. Flynn ,  Prashant Raghu ,  Kyle Grant

    IPC: H01L21/302 ,  H01L21/461 ,  C03C15/00 ,  C03C25/68 ,  B08B3/00 ,  H01L21/02 ,  H01L21/311 ,  H01L21/306

    CPC classification number: H01L21/30604 ,  H01L21/02052 ,  H01L21/31111

    Abstract: Some embodiments include methods of treating semiconductor substrates. The substrates may be exposed to one or more conditions that vary continuously. The conditions may include temperature gradients, concentration gradients of one or more compositions that quench etchant, pH gradients to assist in removing particles, and/or concentration gradients of one or more compositions that assist in removing particles. The continuously varying conditions may be imparted by placing the semiconductor substrates in a bath of flowing rinsing solution, with the bath having at least two feed lines that provide the rinsing solution therein. One of the feed lines may be at a first condition, and the other may be at a second condition that is different from the first condition. The relative amount of rinsing solution provided to the bath by each feed line may be varied to continuously vary the condition within the bath.

    Abstract translation: 一些实施方案包括处理半导体衬底的方法。 衬底可以暴露于连续变化的一个或多个条件。 条件可以包括温度梯度，一种或多种淬灭蚀刻剂的组合物的浓度梯度，有助于除去颗粒的pH梯度和/或一种或多种有助于除去颗粒的组合物的浓度梯度。 可以通过将半导体衬底放置在流动的漂洗溶液浴中来赋予连续变化的条件，浴中具有至少两条在其中提供漂洗溶液的进料管线。 供给管线中的一个可以处于第一状态，另一个可以处于与第一条件不同的第二条件。 可以改变通过每个进料管提供给浴的冲洗溶液的相对量，以连续地改变浴内的状态。

    Memory Circuitry And Methods Used In Forming Memory Circuitry
    20.
    发明公开
    Memory Circuitry And Methods Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240224505A1

    公开(公告)日：2024-07-04

    申请号：US18527091

    申请日：2023-12-01

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  Ying Rui ,  Silvia Borsari ,  Prashant Raghu ,  Elisabeth Barr ,  Yen Ting Lin ,  Albert P. Chan ,  Martin Chen

    IPC: H10B12/00

    CPC classification number: H10B12/33 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482

    Abstract: A method used in forming memory circuitry comprises forming transistors individually comprising one source/drain region and another source/drain region. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Digitline structures are formed that are individually directly electrically coupled to the another source/drain regions of multiple of the transistors. The digitline structures individually comprise a conductive digitline and an insulator material thereatop. The insulator material has a top. First insulating material is formed directly above the tops of the insulator material and laterally-over longitudinal sides of the digitline structures and covers across the one source/drain regions laterally-between immediately-adjacent of the digitline structures. Second insulating material is formed over the first insulating material. The second insulating material has a maximum vertical thickness directly above the digitline structures that is greater than its minimum lateral thickness over the longitudinal sides of the digitline structures. The first insulating material is etched through to expose the one source/drain regions. Storage elements are formed that are individually electrically coupled to individual of the one source/drain regions. Other embodiments, including structure, are disclosed.

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