公开(公告)号：US11728307B2

公开(公告)日：2023-08-15

申请号：US17236499

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Quang Nguyen ,  Christopher Glancey ,  Koustav Sinha ,  Chan H. Yoo

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/1147 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13078 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/3512

Abstract: Semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include a plurality of conductive elements made of a first conductive material having a first elastic modulus. The pillar structure can further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material can have a second elastic modulus less than the first elastic modulus.

公开(公告)号：US20230061955A1

公开(公告)日：2023-03-02

申请号：US17591519

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Koustav Sinha ,  Quang Nguyen ,  Christopher Glancey ,  Shams U. Arifeen

IPC: H01L23/00 ,  H01L23/498

Abstract: A semiconductor package assembly includes a first mounting surface of a package substrate that faces a second mounting surface of a printed circuit board. A first structural element bond pad is mounted to the first mounting surface. A second structural element bond pad is mounted to the second mounting surface, and the first and second structural element bond pads are aligned with each other. A structural element is interconnected with a first solder joint to the first structural element bond pad and interconnected with a second solder joint to the second structural element bond pad. The structural element extends between the first and second structural element bond pads to absorb mechanical shock when a compressive force pushes one of the first and second mounting surfaces toward the other.

公开(公告)号：US20220344295A1

公开(公告)日：2022-10-27

申请号：US17236499

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Shams U. Arifeen ,  Quang Nguyen ,  Christopher Glancey ,  Koustav Sinha ,  Chan H. Yoo

IPC: H01L23/00

Abstract: Semiconductor devices having interconnect structures with conductive elements configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include a plurality of conductive elements made of a first conductive material having a first elastic modulus. The pillar structure can further include a continuous region of a second conductive material at least partially surrounding the plurality of conductive elements. The second conductive material can have a second elastic modulus less than the first elastic modulus.

公开(公告)号：US20230260943A1

公开(公告)日：2023-08-17

申请号：US17674685

申请日：2022-02-17

Applicant: Micron Technology, Inc.

Inventor： Christopher Glancey ,  Shams U. Arifeen ,  Koustav Sinha ,  Quang Nguyen

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/13084 ,  H01L2224/13005 ,  H01L2224/0401 ,  H01L2224/13147 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/16227

Abstract: Semiconductor die assemblies with flexible interconnects, and associated methods and systems are disclosed. The semiconductor die assembly includes a package substrate and a semiconductor die attached to the package substrate through the flexible interconnects. The flexible interconnects include one or more rigid sections and one or more flexible sections, each of which is disposed next to the rigid sections. The flexible sections may include malleable materials with relatively low melting temperatures (e.g., having relatively low modulus at elevated temperatures) such that the flexible interconnects can have reduced flexural stiffness during the assembly process. The malleable materials of the flexible interconnects, through plastic deformation in response to stress generated during the assembly process, may facilitate portions of the flexible interconnects to shift so as to reduce transfer of the stress to other parts of the semiconductor die assembly—e.g., circuitry of the semiconductor die.

公开(公告)号：US11664360B2

公开(公告)日：2023-05-30

申请号：US17566397

申请日：2021-12-30

Applicant: Micron Technology, Inc.

Inventor： Quang Nguyen ,  Christopher Glancey ,  Shams U Arifeen ,  Koustav Sinha

IPC: H01L25/18 ,  H05K1/18 ,  H01L23/00 ,  H01L25/00 ,  H05K3/34 ,  H05K1/02 ,  H05K3/00

CPC classification number: H01L25/18 ,  H01L24/16 ,  H01L25/50 ,  H05K1/0271 ,  H05K1/183 ,  H05K3/3436 ,  H01L2224/16225 ,  H01L2924/15153 ,  H05K3/0017 ,  H05K2201/10159

Abstract: Various embodiments described herein provide for printed circuit boards with one or more spaces for embedding components, which can be used to implement a memory sub-system.

公开(公告)号：US11217576B1

公开(公告)日：2022-01-04

申请号：US17023037

申请日：2020-09-16

Applicant: Micron Technology, Inc.

Inventor： Quang Nguyen ,  Christopher Glancey ,  Shams U Arifeen ,  Koustav Sinha

IPC: H05K1/00 ,  H05K1/18 ,  H05K7/00 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00 ,  H05K1/02 ,  H05K3/34 ,  H05K3/00

Abstract: Various embodiments described herein provide for printed circuit boards with one or more spaces for embedding components, which can be used to implement a memory sub-system.