公开(公告)号：US20220351758A1

公开(公告)日：2022-11-03

申请号：US17748866

申请日：2022-05-19

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/10 ,  G11C29/42 ,  G11C16/10 ,  G11C16/26 ,  G11C7/06

Abstract: The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.

公开(公告)号：US20220101917A1

公开(公告)日：2022-03-31

申请号：US17495423

申请日：2021-10-06

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

IPC: G11C13/00 ,  G11C16/04 ,  G11C7/10 ,  G11C16/28

Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.

公开(公告)号：US11289147B2

公开(公告)日：2022-03-29

申请号：US17165529

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Efrem Bolandrina ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C7/00 ,  G11C11/22

Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.

公开(公告)号：US20220020448A1

公开(公告)日：2022-01-20

申请号：US17387335

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C29/42 ,  G11C29/44 ,  G11C5/02 ,  G11C11/4074 ,  G11C11/4091 ,  G11C29/02

Abstract: Methods, systems, and devices for method for setting a reference voltage for read operations are described. A memory device may perform a first read operation on a set of memory cells using a first reference voltage and detect a first codeword based on performing the first read operation using the first reference voltage. The memory device may compare a first quantity of bits of the first codeword having a first logic value (e.g., a logic value ‘1’) with an expected quantity of bits having the first logic value (e.g., the expected quantity of logic value ‘1’s stored by the set of memory cells). The memory device may determine whether to perform a second read operation on the set of memory cells using a second reference voltage different than the first reference voltage (e.g., greater or less than the first reference voltage) based on the comparing.

公开(公告)号：US20210134342A1

公开(公告)日：2021-05-06

申请号：US17097749

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto

IPC: G11C11/22 ,  G06F13/40

Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.

公开(公告)号：US20190341093A1

公开(公告)日：2019-11-07

申请号：US16507419

申请日：2019-07-10

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto

IPC: G11C11/22

Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.

公开(公告)号：US10446232B2

公开(公告)日：2019-10-15

申请号：US15846373

申请日：2017-12-19

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/22 ,  G11C14/00

Abstract: The present provision includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

公开(公告)号：US09368202B2

公开(公告)日：2016-06-14

申请号：US14713878

申请日：2015-05-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/12 ,  G11C8/08 ,  G11C7/14 ,  G11C7/06 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12

CPC classification number: G11C13/004 ,  G11C7/062 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C29/025 ,  G11C29/028 ,  G11C2013/0052 ,  G11C2013/0054 ,  G11C2029/0409 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2207/063 ,  G11C2213/79

Abstract: Apparatuses, sense circuits, and methods for compensating for a voltage increase on a wordline in a memory is described. An example apparatus includes a bitline, a memory cell coupled to the bitline, a bipolar selector device coupled to the memory cell, a wordline coupled to the bipolar selector device, and a wordline driver coupled to the wordline. The apparatus further includes a model wordline circuit configured to model an impedance of the wordline and an impedance of the wordline driver, and a sense circuit coupled to the bitline and to the model wordline circuit. The sense circuit is configured to sense a state of the memory cell based on a cell current and provide a sense signal indicating a state of the memory cell. The sense circuit is further configured to adjust a bitline voltage responsive to an increase in wordline voltage as modeled by the model wordline circuit.

公开(公告)号：US20150279459A1

公开(公告)日：2015-10-01

申请号：US14740074

申请日：2015-06-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Vimercati ,  Riccardo Muzzetto

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C7/02 ,  G11C7/04 ,  G11C7/14 ,  G11C13/0004 ,  G11C2013/0045 ,  G11C2013/0054

Abstract: This disclosure relates to generating a reference current for a memory device. In one aspect, a non-volatile memory device, such as a phase change memory device, can determine a value of a data digit, such as a bit, stored in a non-volatile memory cell based at least partly on the reference current. The reference current can be generated by mirroring a current at a node that is biased by a voltage bias. A configurable resistance circuit can have a resistance that is configurable. The resistance of the configurable resistance circuit can be in series between the node and a resistive non-volatile memory element. In some embodiments, a plurality of non-volatile memory elements can each be electrically connected in series between the resistance of the configurable resistance circuit and a corresponding selector.

公开(公告)号：US12288592B2

公开(公告)日：2025-04-29

申请号：US17873991

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Michele Maria Venturini ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Christophe Vincent Antoine Laurent ,  Christian Caillat

IPC: G11C29/50

Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.