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    Memory Systems and Memory Programming Methods
    12.
    发明申请
    Memory Systems and Memory Programming Methods 审中-公开

    公开(公告)号：US20190279714A1

    公开(公告)日：2019-09-12

    申请号：US16427229

    申请日：2019-05-30

    Applicant: Micron Technology, Inc.

    Inventor： Richard E. Fackenthal ,  Simone Lombardo

    IPC: G11C13/00

    Abstract: Memory systems and memory programming methods are described. In one arrangement, a memory system includes a memory cell configured to have a plurality of different memory states, an access circuit coupled with the memory cell and configured to provide a first signal to a memory element of the memory cell to program the memory cell from a first memory state to a second memory state, and a current source coupled with the memory cell and configured to generate a second signal which is provided to the memory element of the memory cell after the first signal to complete programming of the memory cell from the first memory state to the second memory state.

    Thin film transistor random access memory
    15.
    发明授权
    Thin film transistor random access memory 有权

    公开(公告)号：US12302545B2

    公开(公告)日：2025-05-13

    申请号：US18369606

    申请日：2023-09-18

    Applicant: Micron Technology, Inc.

    Inventor： Richard E. Fackenthal

    IPC: H10B10/00 ,  H01L23/528 ,  H10D30/01 ,  H10D30/67 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85

    Abstract: Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.

    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES
    16.
    发明申请
    MEMORY DEVICE HAVING 2-TRANSISTOR VERTICAL MEMORY CELL AND SHIELD STRUCTURES 有权

    公开(公告)号：US20240420750A1

    公开(公告)日：2024-12-19

    申请号：US18818295

    申请日：2024-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Alessandro Calderoni ,  Richard E. Fackenthal ,  Duane R. Mills

    IPC: G11C11/404

    Abstract: Some embodiments include apparatuses in which one of such apparatus includes a first memory cell including a first transistor having a first channel region coupled between a data line and a conductive region, and a first charge storage structure located between the first data line and the conductive region, and a second transistor having a second channel region coupled to and located between the first data line and the first charge storage structure; a second memory cell including a third transistor having a third channel region coupled between a second data line and the conductive region, and a second charge storage structure located between the second data line and the conductive region, and a fourth transistor having a fourth channel region coupled to and located between the second data line and the second charge storage structure; a conductive line forming a gate of each of the first, second, third, and fourth transistors; and a conductive structure located between the first and second charge storage structures and electrically separated from the conductive region.

    STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS
    17.
    发明公开
    STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS 审中-公开

    公开(公告)号：US20240071465A1

    公开(公告)日：2024-02-29

    申请号：US17821645

    申请日：2022-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Mingdong Cui ,  Richard E. Fackenthal

    IPC: G11C11/408 ,  G11C5/02 ,  G11C11/4091

    CPC classification number: G11C11/4085 ,  G11C5/025 ,  G11C11/4091

    Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include a gate material operable to modulate a conductivity between the first portions and the second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

    MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES
    18.
    发明公开
    MICROELECTRONIC DEVICES, RELATED ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES 审中-公开

    公开(公告)号：US20230389275A1

    公开(公告)日：2023-11-30

    申请号：US17804234

    申请日：2022-05-26

    Applicant: Micron Technology, Inc.

    Inventor： Fatma Arzum Simsek-Ege ,  Richard E. Fackenthal

    IPC: H01L27/108 ,  H01L23/528

    CPC classification number: H01L27/10805 ,  H01L27/1085 ,  H01L27/10873 ,  H01L23/5283

    Abstract: A microelectronic device comprises a vertical stack of memory cells. The vertical stack of memory cells comprises a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, a conductive pillar structure in electrical communication with the vertical stack of access devices, and an isolated conductive structure in electrical communication with a multiplexer comprising a vertically uppermost access device of the vertical stack of access devices. The microelectronic device further comprises a stack structure comprising conductive structures interleaved with insulative structures, at least some of the conductive structures individually in electrical communication with a memory cell of the vertical stack of memory cells and comprising a gate of an access device of the vertical stack of access devices. Related electronic systems and methods are also described.

    Thin film transistor random access memory
    19.
    发明授权
    Thin film transistor random access memory 有权

    公开(公告)号：US11770923B2

    公开(公告)日：2023-09-26

    申请号：US17191446

    申请日：2021-03-03

    Applicant: Micron Technology, Inc.

    Inventor： Richard E. Fackenthal

    IPC: H10B10/00 ,  H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/786

    CPC classification number: H10B10/125 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66742 ,  H01L29/78642

    Abstract: Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.

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