公开(公告)号：US20170243644A1

公开(公告)日：2017-08-24

申请号：US15589320

申请日：2017-05-08

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Roberto Gastaldi

IPC: G11C13/00

CPC classification number: G11C13/0033 ,  G06F11/1068 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C14/009 ,  G11C16/3418 ,  G11C29/52

Abstract: Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.

公开(公告)号：US09437294B2

公开(公告)日：2016-09-06

申请号：US14717784

申请日：2015-05-20

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Roberto Gastaldi

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2013/0076

Abstract: The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal.

公开(公告)号：US09196359B2

公开(公告)日：2015-11-24

申请号：US14571137

申请日：2014-12-15

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Roberto Gastaldi

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2211/5634 ,  G11C2213/54

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

Abstract translation: 本文公开的主题涉及存储器件，更具体地涉及写入相变存储器的性能。

公开(公告)号：US20140140134A1

公开(公告)日：2014-05-22

申请号：US14165072

申请日：2014-01-27

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Roberto Gastaldi

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.

Abstract translation: 一些实施例包括具有一串存储器单元的装置和方法，导线和双极结型晶体管被配置为选择性地将该串存储器单元耦合到导线。 描述包括附加装置和方法的其它实施例。

公开(公告)号：US20130272063A1

公开(公告)日：2013-10-17

申请号：US13913714

申请日：2013-06-10

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Roberto Gastaldi

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0035 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2211/5634 ,  G11C2213/54

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to write performance of a phase change memory.

公开(公告)号：US10861552B2

公开(公告)日：2020-12-08

申请号：US16362082

申请日：2019-03-22

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Roberto Gastaldi

IPC: G11C16/04 ,  G11C16/10

Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.

公开(公告)号：US20170316831A1

公开(公告)日：2017-11-02

申请号：US15651985

申请日：2017-07-17

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Roberto Gastaldi

IPC: G11C16/04 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.

公开(公告)号：US09711223B2

公开(公告)日：2017-07-18

申请号：US14165072

申请日：2014-01-27

Applicant: Micron Technology, Inc.

Inventor： Paolo Tessariol ,  Roberto Gastaldi

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described.

公开(公告)号：US09047944B2

公开(公告)日：2015-06-02

申请号：US13869512

申请日：2013-04-24

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Roberto Gastaldi

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0047 ,  G11C2013/0057 ,  G11C2013/0076

Abstract: The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include programming a memory cell to an initial data state and determining a data state of the memory cell by applying a programming signal to the memory cell, the programming signal associated with programming memory cells to a particular data state, and determining whether the data state of the memory cell changes from the initial data state to the particular data state during application of the programming signal.

Abstract translation: 本公开包括用于感测电阻变量存储单元的装置和方法。 多个实施例包括将存储器单元编程为初始数据状态，并通过将编程信号施加到存储器单元，将编程信号与编程存储器单元相关联到特定数据状态来确定存储器单元的数据状态，以及确定是否 在应用编程信号期间，存储单元的数据状态从初始数据状态变为特定数据状态。

公开(公告)号：US10311951B2

公开(公告)日：2019-06-04

申请号：US16108828

申请日：2018-08-22

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Roberto Gastaldi

IPC: G11C11/00 ,  G11C13/00 ,  G06F11/10 ,  G11C16/34 ,  G11C14/00 ,  G11C29/52 ,  G11C11/56

Abstract: Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.