公开(公告)号：US09754946B1

公开(公告)日：2017-09-05

申请号：US15210511

申请日：2016-07-14

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Russell A. Benson ,  Brent Gilgen ,  Alex J. Schrinsky ,  Sanh D. Tang ,  Si-Woo Lee

IPC: H01L21/768 ,  H01L27/108

CPC classification number: H01L27/10885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76877 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

公开(公告)号：US20240038588A1

公开(公告)日：2024-02-01

申请号：US17815359

申请日：2022-07-27

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Vinay Nair ,  Russell A. Benson ,  Christopher W. Petz ,  Si-Woo Lee ,  Silvia Borsari ,  Ping Chieh Chiang ,  Luca Fumagalli

IPC: H01L21/768 ,  H01L27/108

CPC classification number: H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. Sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. The sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. Plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. The sacrificial line structures are replaced with additional trenches. Conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures. Conductive line structures are formed within the additional trenches and in contact with the conductive contact structures.

公开(公告)号：US20230345708A1

公开(公告)日：2023-10-26

申请号：US17729450

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Terrence B. McDaniel ,  Russell A. Benson ,  Vinay Nair

IPC: H01L27/108

CPC classification number: H01L27/10885 ,  H01L27/10888 ,  H01L27/10897

Abstract: Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.

公开(公告)号：US20220246622A1

公开(公告)日：2022-08-04

申请号：US17726266

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： Russell A. Benson

IPC: H01L27/108

Abstract: A method used in forming integrated circuitry comprises forming horizontally-spaced conductive vias above a substrate. Conducting material is formed directly above and directly against the conductive vias. The conducting material is patterned to form individual conductive lines that are individually directly above a plurality of the conductive vias that are spaced longitudinally-along the respective individual conductive line. The patterning forms the individual conductive lines to have longitudinally-alternating wider and narrower regions. The wider regions are directly above and directly against a top surface of individual of the conductive vias and are wider in a horizontal cross-section that is at the top surface than are the narrower regions in the horizontal cross-section. The narrower regions are longitudinally-between the wider regions. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20220102348A1

公开(公告)日：2022-03-31

申请号：US17038799

申请日：2020-09-30

Applicant: Micron Technology, Inc.

Inventor： Vinay Nair ,  Silvia Borsari ,  Ryan L. Meyer ,  Russell A. Benson ,  Yi Fang Lee

IPC: H01L27/108 ,  G11C11/402 ,  G11C5/10

Abstract: A method used in forming integrated circuitry comprises forming conductive material over a substrate. The conductive material is patterned into a conductive line that is horizontally longitudinally elongated. The conductive material is vertically recessed in longitudinally-spaced first regions of the conductive line to form longitudinally-spaced conductive pillars that individually are in individual longitudinally-spaced second regions that longitudinally-alternate with the longitudinally-spaced first regions along the conductive line. The conductive pillars project vertically relative to the conductive material in the longitudinally-spaced and vertically-recessed first regions of the conductive line. Electronic components are formed directly above the conductive pillars. Individual of the electronic components are directly electrically coupled to individual of the conductive pillars. Additional methods, including structure independent of method, are disclosed.

公开(公告)号：US11189484B2

公开(公告)日：2021-11-30

申请号：US16723557

申请日：2019-12-20

Applicant: Micron Technology, Inc.

Inventor： Russell A. Benson ,  Silvia Borsari ,  Vinay Nair ,  Ying Rui ,  Somik Mukherjee

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/311

Abstract: Methods, apparatuses, and systems related to a semiconductor nitridation passivation are described. An example method includes performing a dry etch process on a semiconductor structure on a wafer in a semiconductor fabrication process. The method further includes performing a dry strip process on the semiconductor structure. The method further includes performing a first wet strip clean process on the semiconductor. The method further includes performing a second wet strip clean process on the semiconductor. The method further includes performing a nitridation passivation on the semiconductor structure to avoid oxidization of the semiconductor structure. The method further performing a spacer material deposition on the semiconductor structure.

公开(公告)号：US11011378B2

公开(公告)日：2021-05-18

申请号：US16459079

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： Yiping Wang ,  Caizhi Xu ,  Pengyuan Zheng ,  Ying Rui ,  Russell A. Benson ,  Yongjun J. Hu ,  Jaydeb Goswami

IPC: H01L21/033 ,  H01L27/108 ,  H01L21/308

Abstract: Systems, apparatuses, and methods related to atom implantation for reduction of compressive stress are described. An example method may include patterning a working surface of a semiconductor, the working surface having a hard mask material formed over a dielectric material and forming a material having a lower refractive index (RI), relative to a RI of the hard mask material, over the hard mask material. The method may further include implanting atoms through the lower RI material and into the hard mask material to reduce the compressive stress in the hard mask material.

公开(公告)号：US20180019245A1

公开(公告)日：2018-01-18

申请号：US15652724

申请日：2017-07-18

Applicant: Micron Technology, Inc.

Inventor： Guangjun Yang ,  Russell A. Benson ,  Brent Gilgen ,  Alex J. Schrinsky ,  Sanh D. Tang ,  Si-Woo Lee

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10885 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76877 ,  H01L27/10814 ,  H01L27/10855

Abstract: A method of forming an elevationally extending conductor laterally between a pair of conductive lines comprises forming a pair of conductive lines spaced from one another in at least one vertical cross-section. Conductor material is formed to elevationally extend laterally between and cross elevationally over the pair of conductive lines in the at least one vertical cross-section. Sacrificial material is laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section. The sacrificial material is removed from between the elevationally extending conductor material and each of the conductive lines of the pair while the conductor material is crossing elevationally over the pair of conductive lines to form a void space laterally between the elevationally extending conductor material and each of the conductive lines of the pair in the at least one vertical cross-section.

公开(公告)号：US20140252589A1

公开(公告)日：2014-09-11

申请号：US14280829

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： James B. Griffin ,  Russell A. Benson

IPC: H01L23/373

CPC classification number: H01L23/3736 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.

Abstract translation: 在半导体衬底中形成空穴期间耗散电荷的结构和方法。

公开(公告)号：US12069848B2

公开(公告)日：2024-08-20

申请号：US17729450

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Kuo-Chen Wang ,  Terrence B. McDaniel ,  Russell A. Benson ,  Vinay Nair

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/485 ,  H10B12/50

Abstract: Methods, apparatuses, and systems related to a sense line and cell contact for a semiconductor structure are described. An example apparatus includes a first source/drain region and a second source/drain region, where the first source/drain region and the second source/drain region are separated by a channel, a gate opposing the channel, a sense line material coupled to the first source/drain region by a cell contact, where the cell contact is made from a combination of a first polysilicon material and a second polysilicon material, and a storage node coupled to the second source/drain region.