公开(公告)号：US20220231029A1

公开(公告)日：2022-07-21

申请号：US17150020

申请日：2021-01-15

Applicant: Micron Technology, Inc.

Inventor： Sangmin Hwang ,  Kyuseok Lee ,  Christopher G. Wieduwilt

IPC: H01L27/108 ,  H01L27/092 ,  G11C5/06 ,  G11C11/4091 ,  G11C11/408 ,  H01L29/78

Abstract: Some embodiments include an integrated assembly having a CMOS region. Fins extend across the CMOS region and are on a first pitch. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate the CMOS region. Conductive structures are associated with the second region. The conductive structures extend along a second direction different than the first direction. Some of the conductive structures are electrically coupled with the circuit arrangement. The conductive structures are on a second pitch different from the first pitch. A second dimension is a distance across said some of the conductive structures along the first direction, and the second dimension is substantially the same as the first dimension.

公开(公告)号：US20220130831A1

公开(公告)日：2022-04-28

申请号：US17079745

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Sangmin Hwang

IPC: H01L27/108

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines, and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region of the horizontally oriented access devices. The vertically oriented digit lines are formed in direct electrical contact with the first source/drain regions of the horizontally oriented access devices. A vertically oriented body contact line is integrated to form the body contact to the body region of the horizontally oriented access device and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

公开(公告)号：US20150028406A1

公开(公告)日：2015-01-29

申请号：US13948746

申请日：2013-07-23

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Kamal M. Karda ,  Wolfgang Mueller ,  Sourabh Dhir ,  Robert Kerr ,  Sangmin Hwang ,  Haitao Liu

IPC: H01L29/423 ,  H01L29/06 ,  H01L27/108

CPC classification number: H01L27/10823 ,  H01L21/76232 ,  H01L23/528 ,  H01L27/10808 ,  H01L27/10876 ,  H01L29/0649 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.

Abstract translation: 一组凹进的存取栅极线包括其间具有介电沟槽隔离材料的有源区域区域。 沟槽隔离材料包括延伸到有源区域区域的材料的最外表面下方的各个有源区域的相对端的电介质突起。 有源区域材料在电介质突起上是垂直的。 嵌入式栅极线分别横跨有源区域区域延伸并且在电介质沟槽隔离材料内的紧邻端到端相邻有源区域区域的端部之间延伸。 公开了其他阵列，方法也是如此。

公开(公告)号：US20240373624A1

公开(公告)日：2024-11-07

申请号：US18774420

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H10B12/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

公开(公告)号：US12063797B2

公开(公告)日：2024-08-13

申请号：US17513489

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Kyuseok Lee ,  Sangmin Hwang ,  Byung Yoon Kim

IPC: H10B99/00 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H10B99/00 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/092

Abstract: An apparatus includes a substrate and a memory cell array disposed on the substrate. The apparatus also includes a logic cell disposed on the substrate in a peripheral region adjacent the memory cell array. The apparatus further includes a trench isolation region disposed in the substrate in the peripheral region. The trench isolation region either separates a first active area of the logic cell from a second active area of the logic cell or separates the logic cell from an adjacent logic cell. The logic cell includes a connection line that is buried within the trench isolation region. The connection line can be formed as an extension of a buried word line in the memory cell array region during a same fabrication process that forms the corresponding buried word line. By extending the buried word line into the peripheral region, the buried connection line can be formed without additional processing.

公开(公告)号：US12052858B2

公开(公告)日：2024-07-30

申请号：US18131097

申请日：2023-04-05

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H10B12/00 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B12/50 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B12/09 ,  H10B12/30

Abstract: Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

公开(公告)号：US11594536B2

公开(公告)日：2023-02-28

申请号：US17197253

申请日：2021-03-10

Applicant: Micron Technology, Inc.

Inventor： Yong Mo Yang ,  Mohd Kamran Akhtar ,  Huyong Lee ,  Sangmin Hwang ,  Song Guo

IPC: H01L27/092 ,  H01L21/8238 ,  G11C7/06

Abstract: Some embodiments include an integrated assembly having a CMOS region with fins extending along a first direction, and with gating structures extending across the fins. A circuit arrangement is associated with the CMOS region and includes a pair of the gating structures spaced by an intervening region having a missing gating structure. The circuit arrangement has a first dimension along the first direction. A second region is proximate to the CMOS region. Conductive structures are associated with the second region. Some of the conductive structures are electrically coupled with the circuit arrangement. A second dimension is a distance across said some of the conductive structures along the first direction. The conductive structures and the circuit arrangement are aligned such that the second dimension is substantially the same as the first dimension. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220246525A1

公开(公告)日：2022-08-04

申请号：US17165276

申请日：2021-02-02

Applicant: Micron Technology, Inc.

Inventor： Byung Yoon Kim ,  Sangmin Hwang ,  Kyuseok Lee

IPC: H01L23/528 ,  H01L27/108 ,  H01L23/522 ,  H01L21/768

Abstract: Devices, systems, and methods for forming twisted conductive lines are described herein. One method includes: forming a first row and a second row of a first number of vertical conductive line contacts, the vertical contacts in each row are arrayed in a first horizontal direction and the first row is spaced from the second row in a second horizontal direction; forming a number of conductive lines with curved portions, each conductive line making contact with alternating conductive line contacts of the first and second rows of the first number of vertical conductive line contacts; and forming a second number of conductive lines with one or more curved portions, each conductive line making contact with the remaining ones of the conductive line contacts of the first and second rows of the first number of vertical conductive line contacts that have not been contacted by the first number of conductive lines.

公开(公告)号：US20220130834A1

公开(公告)日：2022-04-28

申请号：US17079612

申请日：2020-10-26

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Sangmin Hwang

IPC: H01L27/108 ,  H01L27/06 ,  H01L25/065 ,  G11C11/402

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

公开(公告)号：US20210057418A1

公开(公告)日：2021-02-25

申请号：US16543799

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee ,  Kyuseok Lee ,  Sangmin Hwang

IPC: H01L27/108 ,  G11C5/06

Abstract: A method of forming a microelectronic device comprises forming a spacer structure having a rectangular ring horizontal cross-sectional shape over a transistor, a portion of the spacer structure horizontally overlapping a drain region of the transistor. A masking structure is formed over the spacer structure and the transistor, the masking structure exhibiting an opening therein horizontally overlapping the drain region of the transistor and the portion of the spacer structure. A portion of an isolation structure overlying the drain region of the transistor is removed using the masking structure and the portion of the spacer structure as etching masks to form a trench vertically extending through the isolation structure to the drain region of the transistor. A drain contact structure is formed within the trench in the isolation structure. Microelectronic devices, memory devices, and electronic systems are also described.