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公开(公告)号：US11422826B2
公开(公告)日：2022-08-23
申请号：US16878226
申请日：2020-05-19
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Jonathan D. Harms , Troy D. Larsen , Glen E. Hush , Timothy P. Finkbeiner
IPC: G06F9/4401 , G06F9/38 , G06F12/0868 , G06F13/16 , G06F12/1045
Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.
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公开(公告)号：US11175915B2
公开(公告)日：2021-11-16
申请号：US16156808
申请日：2018-10-10
Applicant: Micron Technology, Inc.
Inventor： Timothy P Finkbeiner , Troy D. Larsen
Abstract: Systems and methods related to implementing vector registers in memory. A memory system for implementing vector registers in memory can include an array of memory cells, where a plurality of rows in the array serve as a plurality of vector registers as defined by an instruction set architecture. The memory system for implementing vector registers in memory can also include a processing resource configured to, responsive to receiving a command to perform a particular vector operation on a particular vector register, access a particular row of the array serving as the particular register to perform the vector operation.
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公开(公告)号：US10664345B2
公开(公告)日：2020-05-26
申请号：US16050585
申请日：2018-07-31
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Troy D. Larsen , Martin L. Culley
Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
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公开(公告)号：US10483978B1
公开(公告)日：2019-11-19
申请号：US16161825
申请日：2018-10-16
Applicant: Micron Technology, Inc.
Inventor： Timothy P Finkbeiner , Troy D. Larsen
IPC: G11C16/26 , H03K19/177 , G06F3/06
Abstract: An example apparatus includes a memory device comprising a plurality of banks of memory cells. A particular bank of memory cells among the plurality of banks includes a system processor resident on a particular bank of the plurality of banks.
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公开(公告)号：US20180336093A1
公开(公告)日：2018-11-22
申请号：US16050585
申请日：2018-07-31
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Troy D. Larsen , Martin L. Culley
Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
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Patent Agency Ranking
公开(公告)号：US09696910B2
公开(公告)日：2017-07-04
申请号：US14867139
申请日：2015-09-28
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Troy D. Larsen , Martin L. Culley , Jeffrey L. Meader , Steve G. Bard , Dean C. Eyres
CPC classification number: G06F3/0608 , G06F3/0661 , G06F3/0673 , H03M7/30 , H03M7/60 , H03M7/6082
Abstract: The present disclosure includes apparatuses and methods for data compression and management. A number of methods include receiving a number of data segments corresponding to a managed unit amount of data, determining a respective compressibility of each of the number of data segments, compressing each of the number of data segments in accordance with its respective determined compressibility, forming a compressed managed unit that includes compressed and/or uncompressed data segments corresponding to the number of data segments corresponding to the managed unit amount of data, and forming a page of data that comprises at least the compressed managed unit.
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公开(公告)号：US09298545B2
公开(公告)日：2016-03-29
申请号：US14255064
申请日：2014-04-17
Applicant: Micron Technology, Inc.
Inventor： Sampath K. Ratnam , Troy D. Larsen , Doyle W. Rivers , Troy A. Manning , Martin L. Culley
CPC classification number: G06F11/1068 , G06F11/10 , G06F11/108 , G11C11/5628 , G11C16/0483
Abstract: Data protection across multiple memory blocks can include writing a first portion of a codeword in a first location of a first memory block and writing a second portion of the codeword in a second location of a second memory block. The second location of the second memory block can be different than the first location of the first memory block.
Abstract translation: 跨越多个存储器块的数据保护可以包括将码字的第一部分写入第一存储器块的第一位置，并将码字的第二部分写入第二存储器块的第二位置。 第二存储器块的第二位置可以不同于第一存储器块的第一位置。
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公开(公告)号：US20250037755A1
公开(公告)日：2025-01-30
申请号：US18763395
申请日：2024-07-03
Applicant: Micron Technology, Inc.
Inventor： Timothy P. Finkbeiner , Glen E. Hush , Troy A. Manning , Troy D. Larsen , Peter L. Brown
IPC: G11C11/4091 , G11C11/4093 , H03K19/20
Abstract: Methods and apparatuses related to using non-zero selection circuitry. For example, the non-zero selection circuitry can determine whether a first word received from a first group of sense amplifiers has at least one bit having a first binary value, such as a logical “1”. In response to the first word being determined to have at least one bit having the first binary value, the first word can be outputted from the non-zero selection circuitry and a second word can be prevented from being outputted (even if the second word is determined to have at least one bit having the first binary value) at least while the first word is being outputted.
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公开(公告)号：US11954499B2
公开(公告)日：2024-04-09
申请号：US17885143
申请日：2022-08-10
Applicant: Micron Technology, Inc.
Inventor： Troy A. Manning , Jonathan D. Harms , Troy D. Larsen , Glen E. Hush , Timothy P. Finkbeiner
IPC: G06F9/4401 , G06F9/38 , G06F12/0868 , G06F12/1045 , G06F13/16
CPC classification number: G06F9/4403 , G06F9/3836 , G06F9/4406 , G06F12/0868 , G06F12/1054 , G06F13/1668 , G06F2212/7201 , G06F2212/7211
Abstract: Methods, systems, and devices for operational code storage for an on-die microprocessor are described. A microprocessor may be formed on-die with a memory array. Operating code for the microprocessor may be stored in the memory array, possibly along with other data (e.g., tracking or statistical data) used or generated by the on-die microprocessor. A wear leveling algorithm may result in some number of rows within the memory array not being used to store user data at any given time, and these rows may be used to store the operating code and possibly other data for the on-die microprocessor. The on-die microprocessor may boot and run based on the operating code stored in memory array.
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公开(公告)号：US11556339B2
公开(公告)日：2023-01-17
申请号：US17454171
申请日：2021-11-09
Applicant: Micron Technology, Inc.
Inventor： Timothy P. Finkbeiner , Troy D. Larsen
Abstract: Systems and methods related to implementing vector registers in memory. A memory system for implementing vector registers in memory can include an array of memory cells, where a plurality of rows in the array serve as a plurality of vector registers as defined by an instruction set architecture. The memory system for implementing vector registers in memory can also include a processing resource configured to, responsive to receiving a command to perform a particular vector operation on a particular vector register, access a particular row of the array serving as the particular register to perform the vector operation.
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