公开(公告)号：US09263341B2

公开(公告)日：2016-02-16

申请号：US14836257

申请日：2015-08-26

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Fawad Ahmed ,  Kamal M. Karda

IPC: H01L21/00 ,  H01L21/8234 ,  H01L21/306

CPC classification number: H01L29/7853 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0607 ,  H01L29/0692 ,  H01L29/42356 ,  H01L29/66795

Abstract: Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.

公开(公告)号：US20150194430A1

公开(公告)日：2015-07-09

申请号：US14148402

申请日：2014-01-06

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Mingtao Li ,  Haitao Liu ,  Deepak Chandra Pandey ,  Mark Fischer

IPC: H01L27/108 ,  H01L29/66 ,  H01L27/105

CPC classification number: H01L27/10879 ,  H01L27/1052 ,  H01L27/10891 ,  H01L29/66613 ,  H01L29/66818 ,  H01L29/785 ,  H01L2029/7857

Abstract: A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. An array of recessed access devices comprises a plurality of pillars protruding from a substrate, and a plurality of channel regions. Each channel region has a width that is less than about 10 nm and couples neighboring pillars to form a plurality of junctionless recessed access devices. A method of forming at least one recessed access device also comprises forming pillars over a substrate, forming at least a channel region coupled with the pillars, the channel region having a relatively narrow width, and forming a gate at least partially surrounding the channel region on at least three sides.

Abstract translation: 一种半导体器件包括凹入的存取器件，其包括第一柱，第二柱，连接第一和第二柱的沟道区，以及设置在沟道区上的栅。 沟道区具有比第一柱和第二柱的宽度窄的宽度。 凹陷进入装置的阵列包括从基板突出的多个支柱和多个通道区域。 每个通道区域具有小于约10nm的宽度并且连接相邻的柱以形成多个无连接的凹入式接入设备。 一种形成至少一个凹陷进入装置的方法还包括在衬底上形成柱，形成至少与柱相连的沟道区，沟道区具有相对较窄的宽度，以及形成至少部分围绕沟道区的栅极 至少三面。

公开(公告)号：US12119269B2

公开(公告)日：2024-10-15

申请号：US17824744

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/792 ,  H10B12/00 ,  H10B51/30 ,  H10B53/30 ,  H10B63/00 ,  H10B99/00 ,  H01L21/311 ,  H01L21/768

CPC classification number: H01L21/823487 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823885 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/7827 ,  H01L29/785 ,  H01L29/78642 ,  H01L29/7926 ,  H10B12/395 ,  H10B51/30 ,  H10B53/30 ,  H10B63/34 ,  H10B99/00 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877

Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

公开(公告)号：US20210391337A1

公开(公告)日：2021-12-16

申请号：US16899339

申请日：2020-06-11

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Venkata Naveen Kumar Neelapala ,  Haitao Liu

IPC: H01L27/108

Abstract: A microelectronic device comprises a first pillar of a semiconductive material, a second pillar of the semiconductive material adjacent to the first pillar of the semiconductive material, an active word line extending between the first pillar and the second pillar, and a passing word line extending on a side of the second pillar opposite the active word line, the passing word line extending into an isolation region within the semiconductive material, the isolation region comprising a lower portion and an upper portion having a substantially circular cross-sectional shape and a larger lateral dimension than the lower portion. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11195560B2

公开(公告)日：2021-12-07

申请号：US16709030

申请日：2019-12-10

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey

IPC: G11C5/06 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200286899A1

公开(公告)日：2020-09-10

申请号：US16294792

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Kamal M. Karda ,  Haitao Liu

IPC: H01L27/108

Abstract: Some embodiments include a method of forming an integrated assembly. Conductive blocks are formed over a construction. Each of the conductive blocks is over a set which includes a pair of storage-element-contact-regions and a digit-line-contact-region. Each of the conductive blocks is entirely laterally surrounded by first insulative material. Central regions of the conductive blocks are removed to split each of the conductive blocks into a first conductive portion over one of the storage-element-contact-regions and a second conductive portion over another of the storage-element-contact-regions. Second insulative material is formed between the first and second conductive portions. Digit-lines are coupled with the digit-line-contact-regions, and storage-elements are coupled with the storage-element-contact-regions.

公开(公告)号：US10756093B1

公开(公告)日：2020-08-25

申请号：US16294792

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Kamal M. Karda ,  Haitao Liu

IPC: H01L27/108 ,  H01L25/18 ,  H01L29/417 ,  G11C11/407

Abstract: Some embodiments include a method of forming an integrated assembly. Conductive blocks are formed over a construction. Each of the conductive blocks is over a set which includes a pair of storage-element-contact-regions and a digit-line-contact-region. Each of the conductive blocks is entirely laterally surrounded by first insulative material. Central regions of the conductive blocks are removed to split each of the conductive blocks into a first conductive portion over one of the storage-element-contact-regions and a second conductive portion over another of the storage-element-contact-regions. Second insulative material is formed between the first and second conductive portions. Digit-lines are coupled with the digit-line-contact-regions, and storage-elements are coupled with the storage-element-contact-regions.

公开(公告)号：US20200258887A1

公开(公告)日：2020-08-13

申请号：US16862122

申请日：2020-04-29

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/167

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.

公开(公告)号：US20200227417A1

公开(公告)日：2020-07-16

申请号：US16248534

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/49 ,  H01L29/167 ,  H01L29/10

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.

公开(公告)号：US10535378B1

公开(公告)日：2020-01-14

申请号：US16040337

申请日：2018-07-19

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Si-Woo Lee

IPC: G11C5/10 ,  H01L27/108 ,  G11C11/401

Abstract: Some embodiments include an integrated assembly which has digit-line-contact-regions laterally spaced from one another by intervening regions. Non-conductive-semiconductor-material is over the intervening regions. Openings extend through the non-conductive-semiconductor-material to the digit-line-contact-regions. Conductive-semiconductor-material-interconnects are within the openings and are coupled with the digit-line-contact-regions. Upper surfaces of the conductive-semiconductor-material-interconnects are beneath a lower surface of the non-conductive-semiconductor-material. Metal-containing-digit-lines are over the non-conductive-semiconductor-material. Conductive regions extend downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects. Some embodiments include methods of forming integrated assemblies.