公开(公告)号：US20210020229A1

公开(公告)日：2021-01-21

申请号：US16514840

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Seungjune Jeon ,  Zhengang Chen ,  Zhenlei Shen ,  Charles See Yeung Kwong

IPC: G11C11/406 ,  G11C11/16

Abstract: A refresh operation can be performed at a memory sub-system The refresh operation can performed at a current frequency. A write count associated with the memory sub-system can be received. A determination can be made as to whether the write count associated with the memory sub-system satisfies a write count threshold. In response to determining that the write count associated with the memory sub-system satisfies the write count threshold, the refresh operation can be performed at an increased frequency relative to the current frequency.

公开(公告)号：US20210012856A1

公开(公告)日：2021-01-14

申请号：US16510454

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhengang Chen

IPC: G11C29/50 ,  G06F11/30

Abstract: A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and determines a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first directional error rate and the second directional error rate satisfies a first threshold criterion and, responsive to the correspondence between the first directional error rate and the second directional error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range.

公开(公告)号：US10783978B1

公开(公告)日：2020-09-22

申请号：US16551950

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Tingjun Xie ,  Steven M. Pope

IPC: G11C16/26 ,  G11C29/12 ,  G11C11/409 ,  G11C29/14 ,  G11C29/50

Abstract: A system includes memory dice, each having a register to store multiple read voltage levels. A processing device is to test each memory die by verification, via access to the multiple read voltage levels, whether each read voltage level falls within a corresponding relative voltage range. The processing device selects an initial read voltage level that achieves bit error rates not satisfying a threshold criterion at one of a first or a second shortest write-to-read (W2R) delay for the memory die and determines a bit error rate, using the initial read voltage level, of storage units of the memory die. The processing device reports the memory die as defective in response to one of: (i) a read voltage level, of the multiple read voltage levels, failing to verify; or (ii) the bit error rate of one or more storage units of the memory die satisfying the threshold criterion.

公开(公告)号：US20200177205A1

公开(公告)日：2020-06-04

申请号：US16205075

申请日：2018-11-29

Applicant: Micron Technology, Inc.

Inventor： Wei Wu ,  Zhenlei Shen ,  Zhengang Chen

IPC: H03M13/15 ,  G06F11/10

Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.

公开(公告)号：US20250110826A1

公开(公告)日：2025-04-03

申请号：US18771829

申请日：2024-07-12

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen

IPC: G06F11/10

Abstract: A processing device in a memory sub-system identifies a plurality of read retry offset voltages having respective check-fail bit counts that are within a target check-fail bit count range for a programming level of a memory device, performs one or more auto-read calibration operations for each of the plurality of read retry offset voltages, and determines respective syndrome weights for sense words read from the memory device using each of the plurality of read retry offset voltages. The processing device further identifies a read retry offset voltage of the plurality of read retry offset voltages having a lowest respective syndrome weight, and performs an error recovery operation using the identified read retry offset voltage.

公开(公告)号：US20240371450A1

公开(公告)日：2024-11-07

申请号：US18637412

申请日：2024-04-16

Applicant: Micron Technology, Inc.

Inventor： Peng Zhang ,  Lei Lin ,  Zhengang Chen ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26

Abstract: A system including a memory device and an operatively coupled processing device to perform operations including: responsive to detecting a power-up event, performing a first read strobe on a first set of a plurality of memory cells addressable by a first wordline, determining a value of a conductivity metric reflecting conductive states of one or more bitlines connected to the first set of the plurality of memory cells, determining, based on the value of the conductivity metric, a read level offset value for a second wordline, wherein the second wordline is adjacent to the first wordline, performing, using the read level offset value, a second read strobe on the second wordline, and responsive to determining that a value of a quality metric produced by the second read strobe satisfies a quality criterion, indicating that a programming operation performed on the second wordline was completed before a power off event.

公开(公告)号：US12067264B2

公开(公告)日：2024-08-20

申请号：US17829920

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Yoav Weinberg

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0655 ,  G06F3/0679

Abstract: A processing device in a memory sub-system receives a request to perform a memory access operation on a memory device, determines a memory segment identifier associated with the memory access operation, and applies a hash function to the memory segment identifier to generate a hashed seed. The processing device further provides the hashed seed to a pseudo-random number generator to generate a randomized string, and performs the memory access operation on the memory device using the randomized string.

公开(公告)号：US20240045759A1

公开(公告)日：2024-02-08

申请号：US18230360

申请日：2023-08-04

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Sivagnanam Parthasarathy

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F3/0673 ,  G06F3/0659 ,  G06F3/0619

Abstract: A method may comprise detecting an error associated with accessing a set of data items. The set of data items are programmed to a respective memory page associated with a stripe of a plurality of stripes. In response to determining that the set of data items comprises one or more codewords, a first data recovery process is performed to recover the one or more codewords based at least in part on RAIN redundancy metadata. In response to determining that the set of data items comprises additional parity metadata, a second data recovery process is performed to recover the additional parity metadata based at least in part on LUN redundancy metadata. In response to determining that the set of data items comprises RAIN redundancy metadata, a first data reconstruction process is performed to regenerate the RAIN redundancy metadata based at least in part on one or more sets of codewords.

公开(公告)号：US20230393765A1

公开(公告)日：2023-12-07

申请号：US17829920

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Yoav Weinberg

IPC: G06F3/06

CPC classification number: G06F3/0623 ,  G06F3/0655 ,  G06F3/0679

Abstract: A processing device in a memory sub-system receives a request to perform a memory access operation on a memory device, determines a memory segment identifier associated with the memory access operation, and applies a hash function to the memory segment identifier to generate a hashed seed. The processing device further provides the hashed seed to a pseudo-random number generator to generate a randomized string, and performs the memory access operation on the memory device using the randomized string.

公开(公告)号：US20230315623A1

公开(公告)日：2023-10-05

申请号：US18206958

申请日：2023-06-07

Applicant: Micron Technology, Inc.

Inventor： Zhengang Chen ,  Jianmin Huang

IPC: G06F12/02 ,  G06F12/14 ,  G06F13/16 ,  H04L9/06 ,  H04L9/08 ,  G11C11/56

CPC classification number: G06F12/0246 ,  G06F12/1408 ,  G06F13/1668 ,  H04L9/0662 ,  H04L9/0869 ,  G11C11/5628 ,  G06F2212/7207

Abstract: Disclosed in some examples are methods, systems, devices, and machine-readable mediums that provide for techniques for scrambling and/or updating meta-data that enable an efficient internal copyback operation. In some examples, improved data distribution techniques decouple the scrambling key from a physical address to allow for copyback operations while maintaining data distribution requirements across a memory device. The controller may generate a seed value that is used by a scrambling algorithm to scramble the host-data and meta-data prior to the data being written. The seed value is then encoded and written to the page with encoded versions of the scrambled user data and meta-data—the random seed is written without scrambling the random seed.