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18 条记录 (耗时 0.028 秒)

    Switch control device
    11.
    发明授权
    Switch control device 失效
    开关控制装置

    公开(公告)号：US08174961B2

    公开(公告)日：2012-05-08

    申请号：US11804468

    申请日：2007-05-18

    申请人： Gwan-Bon Koo ,  Young-Bae Park ,  Sung-Won Yun

    发明人： Gwan-Bon Koo ,  Young-Bae Park ,  Sung-Won Yun

    IPC分类号： H04J7/00 ,  H03M3/00 ,  H03K7/08

    CPC分类号： H03K17/0822 ,  H03K2017/0806

    摘要： The present invention relates to a switch controlling apparatus. The switch controlling apparatus controls a main switch by using a first signal that corresponds to a current flowing to the main switch. The switch controlling apparatus includes a PWM controller for generating a control signal to control turning on/off of the main switch by using the first signal and a clock signal, and a TSD unit for changing the control signal corresponding to heat generated from the main switch. The TSD unit changes a response speed for the heat of the main switch by using the clock signal and the control signal.

    摘要翻译： 开关控制装置技术领域本发明涉及开关控制装置。 开关控制装置通过使用与流过主开关的电流对应的第一信号来控制主开关。 开关控制装置包括：PWM控制器，用于通过使用第一信号和时钟信号产生控制主开关的导通/截止的控制信号;以及TSD单元，用于改变与从主开关产生的热相对应的控制信号 。 TSD单元通过使用时钟信号和控制信号来改变主开关的热量的响应速度。

    Three dimensional semiconductor memory device
    15.
    发明授权
    Three dimensional semiconductor memory device 有权
    三维半导体存储器件

    公开(公告)号：US09030869B2

    公开(公告)日：2015-05-12

    申请号：US13584847

    申请日：2012-08-14

    申请人： Jung-Yun Yun ,  Jong-Yeol Park ,  Chi-Weon Yoon ,  Sung-Won Yun ,  Su-Yong Kim

    发明人： Jung-Yun Yun ,  Jong-Yeol Park ,  Chi-Weon Yoon ,  Sung-Won Yun ,  Su-Yong Kim

    IPC分类号： G11C11/34 ,  G11C7/22 ,  H01L27/115 ,  G11C16/04

    CPC分类号： H01L27/11582 ,  G11C16/0483

    摘要： A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world line pass transistor connected to the memory cell, a second pass transistor group sharing a second well region and comprising a second selection line pass transistor connected to the selection transistor, and a controller that controls the first pass transistor group and the second pass transistor group. The controller applies selected voltages to the first and second well regions during read operation.

    摘要翻译： 三维（3D）半导体存储器件包括存储单元串，每个存储单元串包括至少一个选择晶体管和至少一个存储单元，共享第一阱区的第一级晶体管组，并且包括连接到选择的第一选择线传输晶体管 晶体管和连接到存储单元的第一世界线传输晶体管，第二传输晶体管组共享第二阱区并且包括连接到选择晶体管的第二选择线传输晶体管，以及控制器，其控制第一传输晶体管组和 二级晶体管组。 控制器在读取操作期间将选择的电压施加到第一和第二阱区。

    Memory devices and program methods thereof
    16.
    发明授权
    Memory devices and program methods thereof 有权
    存储器件及其编程方法

    公开(公告)号：US08625367B2

    公开(公告)日：2014-01-07

    申请号：US13476196

    申请日：2012-05-21

    申请人： Sung-Won Yun ,  ChiWeon Yoon ,  Kyung-Hwa Kang ,  JinTae Kim

    发明人： Sung-Won Yun ,  ChiWeon Yoon ,  Kyung-Hwa Kang ,  JinTae Kim

    IPC分类号： G11C5/14 ,  G11C16/00

    CPC分类号： G11C5/025 ,  G11C5/145 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/30

    摘要： Memory devices and program methods thereof, the memory devices including a memory cell array with a three-dimensional structure, a voltage generator configured to supply a pass voltage and a program voltage to the memory cell array, and a control logic configured to make the rising slope of the pass voltage variable with a program loop during a program operation. The memory device may improve a program speed by adjusting the rising slope of the pass voltage according to the program loop.

    摘要翻译： 存储器件及其编程方法，所述存储器件包括具有三维结构的存储单元阵列，被配置为向所述存储单元阵列提供通过电压和编程电压的电压发生器，以及配置为使所述上升的控制逻辑 程序运行期间程序循环的通过电压变量的斜率。 存储器件可以通过根据程序循环调整通过电压的上升沿来提高编程速度。

    Nonvolatile memory device with 3D memory cell array
    17.
    发明授权
    Nonvolatile memory device with 3D memory cell array 有权
    具有3D存储单元阵列的非易失性存储器件

    公开(公告)号：US08570808B2

    公开(公告)日：2013-10-29

    申请号：US13186987

    申请日：2011-07-20

    申请人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    发明人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3454 ,  H01L27/11582 ,  H01L29/7926

    摘要： A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

    摘要翻译： 非易失性存储器件包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压信号的电压发生器电路，以及 行选择电路，其将所述第一电压信号同时施加到所选择的字线，并将所述第二电压信号施加到未选择的字线。 所选择的字线和未选字线具有不同的电阻，而第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。

    NONVOLATILE MEMORY DEVICE WITH 3D MEMORY CELL ARRAY
    18.
    发明申请
    NONVOLATILE MEMORY DEVICE WITH 3D MEMORY CELL ARRAY 有权
    具有3D存储单元阵列的非易失性存储器件

    公开(公告)号：US20120033501A1

    公开(公告)日：2012-02-09

    申请号：US13186987

    申请日：2011-07-20

    申请人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    发明人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3454 ,  H01L27/11582 ,  H01L29/7926

    摘要： Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

    摘要翻译： 公开了一种非易失性存储器件，其包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压的电压发生器电路 信号和行选择电路，其将第一电压信号同时施加到所选字线，并将第二电压信号施加到未选字线。 所选择的字线和未选择的字线具有不同的电阻，但是第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。