公开(公告)号：US20180040426A1

公开(公告)日：2018-02-08

申请号：US15669044

申请日：2017-08-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro WAKASHIMA ,  Yuta SAITO ,  Kohei SHIMADA ,  Naobumi IKEGAMI

IPC: H01G4/248 ,  H01G4/12 ,  H05K1/18 ,  H01G4/30

CPC classification number: H01G4/248 ,  H01G2/06 ,  H01G4/1245 ,  H01G4/232 ,  H01G4/30 ,  H01G4/38 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/10015 ,  Y02P70/611

Abstract: An electronic component is able to be mounted on a mounting substrate including a pair of first edge portions that faces each other, and a pair of second edge portions that is perpendicular or substantially perpendicular to the pair of first edge portions and faces each other. The mounting substrate has a structure that allows at least any one of the electronic component, a first electronic component, and a second electronic component, to be mounted thereon. When a dimension of the first electronic component in a length direction is designated as L1, a dimension of the first electronic component in a width direction is designated as W1, a dimension of the second electronic component in the length direction is designated as L2, and a dimension of the second electronic component in the width direction is designated as W2, a dimension of the electronic component in the width direction is any one of W1 and W2. A dimension of the electronic component in the length direction is L2 when the dimension of the electronic component in the width direction is W1, and is L1 when the dimension of the electronic component in the width direction is W2.

公开(公告)号：US20240087814A1

公开(公告)日：2024-03-14

申请号：US18519243

申请日：2023-11-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta KUROSU ,  Yuta SAITO ,  Masahiro WAKASHIMA ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/232 ,  H01G4/248

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/1218 ,  H01G4/2325 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.

公开(公告)号：US20230352243A1

公开(公告)日：2023-11-02

申请号：US18218300

申请日：2023-07-05

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/008 ,  H01G4/12 ,  H01G4/012

CPC classification number: H01G4/30 ,  H01G4/008 ,  H01G4/1218 ,  H01G4/012

Abstract: In a multilayer ceramic capacitor, a positional deviation in a lamination direction between end portions in a width direction intersecting the lamination direction and a length direction, of two of internal electrode layers adjacent to each other in the lamination direction, is about 5 μm or less. A connection ratio N1/N0 at the middle portion thereof, and a connection ratio N2/N0 at the end portion thereof are about 90% or more, respectively, and a difference between N1/N0 and N2/N0 is about 10% or less.

公开(公告)号：US20230178305A1

公开(公告)日：2023-06-08

申请号：US18103054

申请日：2023-01-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta KUROSU ,  Yuta SAITO ,  Masahiro WAKASHIMA ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/248 ,  H01G4/12 ,  H01G4/008

CPC classification number: H01G4/30 ,  H01G4/2325 ,  H01G4/248 ,  H01G4/1218 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.

公开(公告)号：US20220102077A1

公开(公告)日：2022-03-31

申请号：US17487349

申请日：2021-09-28

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/008

Abstract: In a multilayer ceramic capacitor, a positional deviation in a lamination direction between end portions in a width direction intersecting the lamination direction and a length direction, of two of internal electrode layers adjacent to each other in the lamination direction, is about 5 μm or less. A connection ratio N1/N0 at the middle portion thereof, and a connection ratio N2/N0 at the end portion thereof are about 90% or more, respectively, and a difference between N1/N0 and N2/N0 is about 10% or less.

公开(公告)号：US20240105391A1

公开(公告)日：2024-03-28

申请号：US18524673

申请日：2023-11-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Keita KITAHARA ,  Yuta SAITO ,  Noriyuki OOKAWA ,  Riyousuke AKAZAWA ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA ,  Yuta KUROSU ,  Akito MORI

IPC: H01G4/232 ,  H01G4/008 ,  H01G4/12 ,  H01G4/30

CPC classification number: H01G4/2325 ,  H01G4/008 ,  H01G4/1227 ,  H01G4/30

Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, base electrode layers respectively provided on both end surfaces of the multilayer body in a length direction intersecting a lamination direction, and each connected to the internal electrode layers and each including glass and copper, and plated layers respectively provided on an outer side of the base electrode layers. A protective layer including sulfur is provided between the glass included in the base electrode layers and the plated layers.

公开(公告)号：US20210202177A1

公开(公告)日：2021-07-01

申请号：US17131888

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta KUROSU ,  Yuta SAITO ,  Masahiro WAKASHIMA ,  Daiki FUKUNAGA ,  Yu TSUTSUI

IPC: H01G4/30 ,  H01G4/232 ,  H01G4/008 ,  H01G4/12 ,  H01G4/248

Abstract: A multilayer ceramic capacitor includes a second alloy portion including one metal element provided in a greatest amount among metal elements of an internal electrode layer, and one or more metal elements among a metal group including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y is provided between a second dielectric ceramic layer and a first internal electrode layer, and between a second dielectric ceramic layer and a second internal electrode layer, respectively.

公开(公告)号：US20210202171A1

公开(公告)日：2021-07-01

申请号：US17131893

申请日：2020-12-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yu TSUTSUI ,  Yuta KUROSU ,  Daiki FUKUNAGA ,  Yuta SAITO ,  Masahiro WAKASHIMA

IPC: H01G4/232 ,  H01G4/30 ,  H01G4/248 ,  H01G4/12

Abstract: A multilayer ceramic capacitor includes, in at least one of a region between an end of a first internal electrode layer which is not connected to a second external electrode and the second external electrode, and a region between an end of a second internal electrode layer which is not connected to a first external electrode and the first external electrode, in a length direction, a defect portion provided on a plane including a stacking direction and a width direction, such that the defect portion is located between the first dielectric ceramic layers in the stacking direction and is located between the second dielectric ceramic layer and the third dielectric ceramic layer in the width direction.

公开(公告)号：US20210098191A1

公开(公告)日：2021-04-01

申请号：US16988754

申请日：2020-08-10

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuta SAITO ,  Akito MORI ,  Takefumi TAKAHASHI ,  Masahiro WAKASHIMA

IPC: H01G4/232 ,  H01G4/30 ,  H01G4/12 ,  H01G4/008

Abstract: A multilayer ceramic capacitor includes a laminate including dielectric layers and internal electrode layers laminated together in a lamination direction, and a pair of external electrodes on both end surfaces of the laminate, the external electrodes being connected to the internal electrode layers, wherein a barrier is provided on a widthwise end of at least one internal electrode layer, the barrier having a thickness that decreases from the widthwise end of the internal electrode layer toward a side margin in a width direction, a void is defined by the widthwise end of the internal electrode layer, the barrier, and the side margin, and the barrier contains Ni and Sn.

公开(公告)号：US20180042122A1

公开(公告)日：2018-02-08

申请号：US15669042

申请日：2017-08-04

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masahiro WAKASHIMA ,  Yuta SAITO ,  Kohei SHIMADA ,  Naobumi IKEGAMI

IPC: H05K3/34 ,  H01G4/12 ,  H01G4/005 ,  H05K1/02 ,  H01G2/06 ,  H05K1/18 ,  H01G4/232

CPC classification number: H05K3/3442 ,  H01G2/065 ,  H01G4/005 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30 ,  H01G4/38 ,  H01G4/40 ,  H05K1/0271 ,  H05K1/0295 ,  H05K1/181 ,  H05K2201/10015 ,  H05K2201/10522 ,  Y02P70/611

Abstract: An electronic component is able to be mounted on a mounting substrate on which a first electronic component and a second electronic component are able to be mounted. When dimensions of the first electronic component and the second electronic component in a width direction is designated as W1 and W2, respectively, and dimensions of the first electronic component and the second electronic component in a length direction are designated as L1 and L2, respectively, dimensions of the electronic component in the width direction and the length direction are any one of combinations of W1 and L2, and of W2 and L1. The electronic component includes a third laminate including a pair of third principal surfaces, a pair of third side surfaces, and a pair of third end surfaces, and a pair of third external electrodes. Each of the pair of third external electrodes includes a fired layer, and a resin layer provided on an external surface of the fired layer. On each of the pair of third principal surfaces and on each of the pair of third side surfaces, a length of the resin layer along the length direction from a corresponding one of the third end surfaces to a leading end of the resin layer is less than a length of the fired layer along the length direction from a corresponding one of the third end surfaces to a leading end of the fired layer.