Compact wide band, flared horn antenna with launchers for generating circular polarized sum and difference patterns
    12.
    发明授权
    Compact wide band, flared horn antenna with launchers for generating circular polarized sum and difference patterns 有权
    紧凑的宽带,喇叭喇叭天线,具有发射器,用于产生圆极化和和差模式

    公开(公告)号:US09431715B1

    公开(公告)日:2016-08-30

    申请号:US14818122

    申请日:2015-08-04

    CPC classification number: H01Q13/02 H01Q1/48 H01Q13/025

    Abstract: A flared feed horn including a plurality of signal lines deposited on a bottom surface of a substrate and forming part of a TE11 sum mode launcher, a ground plane deposited a top surface of the substrate, and an outer conductor electrically coupled to the ground plane and having an internal chamber, where the conductor includes a flared portion and a cylindrical portion. The outer conductor includes an opening opposite to the substrate defining an aperture of the feed horn. The feed horn also includes an embedded conductor positioned within the chamber and being coaxial with the outer conductor, where the embedded conductor is in electrical contact with the plurality of signal lines. The feed horn also includes a TE12 difference mode launcher electrically coupled to the outer conductor proximate the aperture.

    Abstract translation: 一种扩口式馈电喇叭,包括沉积在基板的底表面上并形成TE11和模式发射器的一部分的多条信号线,沉积基板的顶表面的接地平面和电耦合到接地平面的外导体, 具有内部腔室,其中导体包括扩口部分和圆柱形部分。 外部导体包括与衬底相对的开口,该开口限定馈电喇叭的孔。 馈电喇叭还包括位于室内并与外部导体同轴的嵌入式导体,其中嵌入式导体与多条信号线电接触。 馈电喇叭还包括电耦合到靠近孔径的外导体的TE12差分模式发射器。

    CHANNELIZED FILTER USING SEMICONDUCTOR FABRICATION

    公开(公告)号:US20240047388A1

    公开(公告)日:2024-02-08

    申请号:US18382598

    申请日:2023-10-23

    CPC classification number: H01L23/66 H01P1/20327 H01L2223/6627 H01L2223/6655

    Abstract: A semiconductor technology implemented high-frequency channelized filter includes a dielectric substrate with metal traces disposed on one of two major surfaces of the substrate. An input and output port disposed on the substrate and one of the metal traces carrying a high-frequency signal to be filtered between the input and output port. Other of the metal traces are connected to the one metal trace at intervals along the length of the one metal trace each providing a reactance to the high-frequency signal where the reactance varies with frequency and additional traces of the metal traces serving as a reference ground for the one metal trace and the other metal traces. A silicon enclosure mounted to the substrate with a first planar surface with cavities in the enclosure that extend through the first surface, and internal walls within the silicon enclosure defining the cavities. A layer of conductive metal covers the first planar surface, cavities and the internal walls. The silicon enclosure having substantially continuous areas of metal on the first planar surface about the periphery of the silicon enclosure that engage corresponding areas of the additional traces about the periphery of the substrate. The cavities surround the respective other metal traces with the internal cavity walls engaging the additional traces adjacent the respective other metal traces to individually surround each of the other metal traces with a conductive metal thereby providing electromagnetic field isolation between each of the other metal traces.

    MICROELECTRONICS H-FRAME DEVICE
    15.
    发明申请

    公开(公告)号:US20220289559A1

    公开(公告)日:2022-09-15

    申请号:US17198700

    申请日:2021-03-11

    Abstract: A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.

    Channelized filter using semiconductor fabrication

    公开(公告)号:US12119313B2

    公开(公告)日:2024-10-15

    申请号:US18382598

    申请日:2023-10-23

    CPC classification number: H01L23/66 H01P1/20327 H01L2223/6627 H01L2223/6655

    Abstract: A semiconductor technology implemented high-frequency channelized filter includes a dielectric substrate with metal traces disposed on one of two major surfaces of the substrate. An input and output port disposed on the substrate and one of the metal traces carrying a high-frequency signal to be filtered between the input and output port. Other of the metal traces are connected to the one metal trace at intervals along the length of the one metal trace each providing a reactance to the high-frequency signal where the reactance varies with frequency and additional traces of the metal traces serving as a reference ground for the one metal trace and the other metal traces. A silicon enclosure mounted to the substrate with a first planar surface with cavities in the enclosure that extend through the first surface, and internal walls within the silicon enclosure defining the cavities. A layer of conductive metal covers the first planar surface, cavities and the internal walls. The silicon enclosure having substantially continuous areas of metal on the first planar surface about the periphery of the silicon enclosure that engage corresponding areas of the additional traces about the periphery of the substrate. The cavities surround the respective other metal traces with the internal cavity walls engaging the additional traces adjacent the respective other metal traces to individually surround each of the other metal traces with a conductive metal thereby providing electromagnetic field isolation between each of the other metal traces.

    Channelized filter using semiconductor fabrication

    公开(公告)号:US11373965B2

    公开(公告)日:2022-06-28

    申请号:US16916644

    申请日:2020-07-17

    Abstract: An exemplary semiconductor technology implemented channelized filter includes a dielectric substrate with semiconductor fabricated metal traces on one surface, and input and output ports. A signal trace connected between the input and output port carries the signal to be filtered. Filter traces connect at intervals along the length of the signal trace to provide a reactance that varies with frequency. Ground traces provide a reference ground. A silicon enclosure with semiconductor fabricated cavities has a metal layer deposited over it. The periphery of the enclosure is dimensioned to engage corresponding ground traces about the periphery of the substrate. Walls of separate cavities enclose each of the filter traces to individually surround each thereby providing electromagnetic field isolation. Metal-to-metal conductive bonds are formed between cavity walls that engage the ground traces to establish a common reference ground. The filter traces preferably meander to minimize the footprint area of the substrate.

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