-
公开(公告)号：US09431962B2
公开(公告)日：2016-08-30
申请号：US14588544
申请日：2015-01-02
Applicant: NXP B.V.
Inventor： Robert Rutten , Lucien Johannes Breems , Jan van Sinderen
CPC classification number: H03D7/1466 , H03D3/009 , H04B1/16 , H04B1/30 , H04B2001/305 , H04L27/3863
Abstract: An RF reception system and method uses IF quadrature mixing, in which there is further mixing and channel filtering in the digital domain, to isolate a frequency of interest. A coefficient estimator is used for generating a phase correction coefficient and an amplitude correction coefficient from filtered in-phase and quadrature desired signals and from filtered in-phase and quadrature image signals.
Abstract translation: RF接收系统和方法使用IF正交混合，其中在数字域中进一步进行混合和信道滤波，以隔离感兴趣的频率。 系数估计器用于从滤波的同相和正交期望信号以及滤波的同相和正交图像信号中产生相位校正系数和幅度校正系数。
-
公开(公告)号：US09143158B2
公开(公告)日：2015-09-22
申请号：US14268409
申请日：2014-05-02
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems
IPC: H03M3/00
Abstract: A sigma-delta modulator (300) comprising a first filter stage (304); a second filter stage (306) in series with the first filter stage (304); a first feedback path (311) between the output of the second filter stage (306) and the input to the second filter stage (306), the first feedback (311) comprising a first gain stage (308, 308′) such that the first feedback path (311) is configured to provide a first gain value; and a second feedback path (313) between the output of the second filter stage (306) and the input to the first filter stage (304), the second feedback path (313) comprising a second gain stage (309; 310′) such that the second feedback path (313) is configured to provide a second gain value. The first gain value is different to the second gain value.
Abstract translation: 包括第一滤波器级（304）的Σ-Δ调制器（300） 与所述第一过滤器级（304）串联的第二过滤器级（306）; 在第二滤波器级（306）的输出与第二滤波级（306）的输入端之间的第一反馈路径（311），第一反馈（311）包括第一增益级（308,308'），使得 第一反馈路径（311）被配置为提供第一增益值; 以及在第二滤波器级（306）的输出与第一滤波级（304）的输入之间的第二反馈路径（313），第二反馈路径（313）包括第二增益级（309; 310'）， 第二反馈路径（313）被配置为提供第二增益值。 第一增益值与第二增益值不同。
-
公开(公告)号：US20150171888A1
公开(公告)日：2015-06-18
申请号：US14558217
申请日：2014-12-02
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems
IPC: H03M3/00
Abstract: Proposed is a sigma-delta modulator circuit. The circuit comprises a loopfilter having at least one integrator or resonator section; and a feed-forward path adapted to provide a feed-forward signal to the output of the at least one integrator or resonator section via a filter.
Abstract translation: 提出了一种Σ-Δ调制器电路。 该电路包括具有至少一个积分器或谐振器部分的环路滤波器; 以及前馈路径，其适于经由滤波器向所述至少一个积分器或谐振器部分的输出提供前馈信号。
-
公开(公告)号：US11967967B2
公开(公告)日：2024-04-23
申请号：US17807454
申请日：2022-06-17
Applicant: NXP B.V.
Inventor： Qilong Liu , Shagun Bajoria , Lucien Johannes Breems
CPC classification number: H03M1/0604 , H03M1/0626 , H03M1/0687 , H03M1/502
Abstract: A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.
-
公开(公告)号：US20240048150A1
公开(公告)日：2024-02-08
申请号：US17880868
申请日：2022-08-04
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
CPC classification number: H03M3/354
Abstract: A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.
-
Patent Agency Ranking
公开(公告)号：US20230412180A1
公开(公告)日：2023-12-21
申请号：US17807454
申请日：2022-06-17
Applicant: NXP B.V.
Inventor： Qilong Liu , Shagun Bajoria , Lucien Johannes Breems
CPC classification number: H03M1/0604 , H03M1/0687 , H03M1/0626 , H03M1/502
Abstract: A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.
-
公开(公告)号：US20210126648A1
公开(公告)日：2021-04-29
申请号：US17065731
申请日：2020-10-08
Applicant: NXP B.V.
Inventor： Chenming Zhang , Lucien Johannes Breems , Muhammed Bolatkale
IPC: H03M3/00
Abstract: A N-bit continuous-time sigma-delta modulator, SDM, (800) includes an input configured to receive an input analog signal (302); a first summing junction (304) configured to subtract a feedback analog signal (303) from the input analog signal (302); a loop filter (306) configured to filter an output signal from the first summing junction (304): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal (309) to a digital output signal (314) where each 1-bit ADC comprises at least one pair of comparator latches (336, 356); and a feedback path (316) for routing the digital output signal to the first summing junction (304). The feedback path (316) includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal (314) to an analog form. The ADC comprises or is operably coupled to, a calibration circuit (650, 840) coupled to an input and an output of the at least one pair of comparator latches (336, 356) and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches (336, 356) in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.
-
公开(公告)号：US10812119B1
公开(公告)日：2020-10-20
申请号：US16445924
申请日：2019-06-19
Applicant: NXP B.V.
Abstract: Interference cancellation is provided, according to certain aspects, by a filter, a signal detection circuit, synthesis circuitry and signal-generation circuitry. The filter is used to filter an incoming signal having an associated signal-to-noise metric and to output therefrom a filtered signal having an interference attribute of the incoming signal by amplification and/or isolation. The signal detection circuit is used to detect the interference attribute in the filtered signal. The synthesis circuitry is used to synthesize interference in the incoming signal based on the interference attribute. The signal-generation circuitry is used to generate, in response to the synthesized interference in the incoming signal, a filtered version of the incoming signal which provides an improved signal-to-noise metric.
-
公开(公告)号：US10164807B2
公开(公告)日：2018-12-25
申请号：US15481038
申请日：2017-04-06
Applicant: NXP B.V.
Inventor： Muhammed Bolatkale , Lucien Johannes Breems
Abstract: A receiver circuit comprising: an input terminal configured to receive an input-signal; a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal; a feedforward-DAC configured to provide a feedforward-analog-signal based on the feedforward-digital-signal; a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analog-signal and the input-signal; an error-LNA configured to provide an amplified-error-signal based on the error-signal; an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal; a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal.
-
公开(公告)号：US20140333462A1
公开(公告)日：2014-11-13
申请号：US14268409
申请日：2014-05-02
Applicant: NXP B.V.
Inventor： Lucien Johannes Breems
IPC: H03M3/00
Abstract: A sigma-delta modulator (300) comprising a first filter stage (304); a second filter stage (306) in series with the first filter stage (304); a first feedback path (311) between the output of the second filter stage (306) and the input to the second filter stage (306), the first feedback (311) comprising a first gain stage (308, 308′) such that the first feedback path (311) is configured to provide a first gain value; and a second feedback path (313) between the output of the second filter stage (306) and the input to the first filter stage (304), the second feedback path (313) comprising a second gain stage (309; 310′) such that the second feedback path (313) is configured to provide a second gain value. The first gain value is different to the second gain value.
Abstract translation: 包括第一滤波器级（304）的Σ-Δ调制器（300） 与所述第一过滤器级（304）串联的第二过滤器级（306）; 在第二滤波器级（306）的输出与第二滤波级（306）的输入端之间的第一反馈路径（311），第一反馈（311）包括第一增益级（308,308'），使得 第一反馈路径（311）被配置为提供第一增益值; 以及在第二滤波器级（306）的输出与第一滤波级（304）的输入之间的第二反馈路径（313），第二反馈路径（313）包括第二增益级（309; 310'）， 第二反馈路径（313）被配置为提供第二增益值。 第一增益值与第二增益值不同。
-
-
-
-
-
-
-
-
-
Search Results
39
records
(took 0.024 seconds)
