公开(公告)号：US11640947B2

公开(公告)日：2023-05-02

申请号：US17333837

申请日：2021-05-28

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L23/00 ,  C09D5/24 ,  C09D179/04 ,  C09D179/08 ,  G03F7/09

Abstract: A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.

公开(公告)号：US11935753B2

公开(公告)日：2024-03-19

申请号：US17546449

申请日：2021-12-09

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L21/283 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/283 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/05558 ,  H01L2924/3511

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

公开(公告)号：US20230378107A1

公开(公告)日：2023-11-23

申请号：US17664117

申请日：2022-05-19

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Yufu Liu ,  Tsung Nan Lo ,  Wen Hung Huang

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L21/56 ,  H01L24/03 ,  H01L2224/0233 ,  H01L2224/0401 ,  H01L2224/02311

Abstract: A semiconductor device package includes a semiconductor device and an electrically conductive pad disposed in contact with a surface of the semiconductor device. The semiconductor device package further includes a redistribution layer (RDL) formed over the electrically conductive pad and the surface of the semiconductor device, and an electrical connector disposed over and electrically coupled to the RDL. The RDL includes a first passivation layer disposed over a surface of the semiconductor device and the electrically conductive pad, and further includes an RDL trace. The RDL trace includes a first portion in contact with the electrically conductive pad, a second portion in contact with one of the electrical connector or an underlying metallization layer in contact with the electrical connector, and a third portion having a non-planar and undulating configuration relative to the surface of the semiconductor device.

公开(公告)号：US12288770B2

公开(公告)日：2025-04-29

申请号：US17660441

申请日：2022-04-25

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Norazham Mohd Sukemi ,  Chin Teck Siong ,  Tsung Nan Lo ,  Wen Hung Huang

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.

公开(公告)号：US20250069903A1

公开(公告)日：2025-02-27

申请号：US18236481

申请日：2023-08-22

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Chin Teck Siong ,  Pey Fang Hiew ,  Wen Hung Huang

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/552

Abstract: A method of forming a semiconductor device is provided. The method includes forming a redistribution layer (RDL) substrate over an active side of a semiconductor die. The RDL substrate includes a plurality of under-bump metallization (UBM) structures. A die pad of a leadframe is affixed on a backside of the semiconductor die. The leadframe includes a plurality of leads having a first portion of each lead connected to the die pad and a second portion of each lead extending vertically along sidewalls of the semiconductor die toward a plane of the RDL substrate. An encapsulant encapsulates the semiconductor die and the leadframe, a lead tip portion of each lead is exposed through the encapsulant.

公开(公告)号：US12198998B2

公开(公告)日：2025-01-14

申请号：US17546398

申请日：2021-12-09

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Che Ming Fang ,  Yufu Liu ,  Wen Hung Huang

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.

公开(公告)号：US12080601B2

公开(公告)日：2024-09-03

申请号：US17377507

申请日：2021-07-16

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Yufu Liu

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/3185 ,  H01L24/13 ,  H01L24/20 ,  H01L2224/13024 ,  H01L2224/214 ,  H01L2924/18162

Abstract: Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.

公开(公告)号：US20230369168A1

公开(公告)日：2023-11-16

申请号：US17740554

申请日：2022-05-10

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Chin Teck Siong ,  Wen Hung Huang

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/481 ,  H01L24/19 ,  H01L21/565 ,  H01L24/20 ,  H01L2224/214 ,  H01L2224/211 ,  H01L2224/2105 ,  H01L2224/2101 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2924/3511 ,  H01L2924/3025

Abstract: An integrated circuit (IC) package includes one or more microelectronic devices disposed between a first side and an opposing second side of the IC package and further includes a metal frame structure comprising a metal layer disposed at the second side, an embedded ground plane (EGP) structure encircling the one or more microelectronic devices, and a set of stacked conductive structures extending from the EGP structure to the first side through a set of one or more redistribution layers at the first side. The IC package further can include an array of package contacts disposed at the first side and an encapsulant layer encapsulating the one or more microelectronic devices in a volume defined by an inner sidewall of the EGP structure.

公开(公告)号：US20230343749A1

公开(公告)日：2023-10-26

申请号：US17660441

申请日：2022-04-25

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Norazham Mohd Sukemi ,  Chin Teck Siong ,  Tsung Nan Lo ,  Wen Hung Huang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L23/49816 ,  H01L24/92 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/48227 ,  H01L2224/92247

Abstract: Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.

公开(公告)号：US20230187211A1

公开(公告)日：2023-06-15

申请号：US17546449

申请日：2021-12-09

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L21/283 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L21/283 ,  H01L24/03 ,  H01L24/11 ,  H01L21/78 ,  H01L24/05 ,  H01L2224/02331 ,  H01L2224/0231 ,  H01L2224/05558 ,  H01L2924/3511

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.