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    OPTICAL INTERCONNECT FABRICS AND OPTICAL SWITCHES
    11.
    发明申请
    OPTICAL INTERCONNECT FABRICS AND OPTICAL SWITCHES 有权
    光学互连织物和光学开关

    公开(公告)号：US20130058607A1

    公开(公告)日：2013-03-07

    申请号：US13697760

    申请日：2010-05-19

    申请人： Nathan Lorenzo Binkert ,  Moray McLaren ,  Michael Renne Ty Tan ,  Alan Lynn Davis

    发明人： Nathan Lorenzo Binkert ,  Moray McLaren ,  Michael Renne Ty Tan ,  Alan Lynn Davis

    IPC分类号： G02B6/28 ,  G02B6/35

    CPC分类号： G02B6/43

    摘要： Optical interconnect fabrics and optical switches are disclosed. In one aspect, an optical interconnect fabric comprises one or more bundles of optical broadcast buses. Each optical broadcast bus is optically coupled at one end to a node and configured to transmit optical signals generated by the node. The optical fabric also includes a number of optical tap arrays distributed along each bundle of optical broadcast buses. Each optical tap array is configured to divert a portion of the optical power associated with the optical signals carried by a bundle of optical broadcast buses to one of the nodes.

    摘要翻译： 公开了光互连结构和光开关。 在一个方面，光学互连结构包括一个或多个光学广播总线束。 每个光学广播总线在一端光耦合到节点并且被配置为传送由节点产生的光信号。 光学结构还包括沿着每束光学广播总线分布的多个光学抽头阵列。 每个光抽头阵列被配置为将与由一束光学广播总线携带的光信号相关联的光功率的一部分转移到节点之一。

    RESONATOR SYSTEMS AND METHODS FOR TUNING RESONATOR SYSTEMS
    12.
    发明申请
    RESONATOR SYSTEMS AND METHODS FOR TUNING RESONATOR SYSTEMS 有权
    用于调谐谐振器系统的谐振器系统和方法

    公开(公告)号：US20120105177A1

    公开(公告)日：2012-05-03

    申请号：US12915598

    申请日：2010-10-29

    申请人： Moray McLaren ,  Raymond G. Beausoleil ,  Marco Fiorentino ,  Nathan Lorenzo Binkert ,  Norman Paul Jouppi ,  Alan Lynn Davis

    发明人： Moray McLaren ,  Raymond G. Beausoleil ,  Marco Fiorentino ,  Nathan Lorenzo Binkert ,  Norman Paul Jouppi ,  Alan Lynn Davis

    IPC分类号： H04B3/04 ,  H01P7/00

    CPC分类号： H01P7/088 ,  G02F1/0147 ,  G02F2203/15 ,  H01P1/2084

    摘要： Tunable resonator systems and methods for tuning resonator systems are disclosed. In one aspect, a resonator system includes an array of resonators disposed adjacent to a waveguide, at least one temperature sensor located adjacent to the array of resonators, and a resonator control electronically connected to the at least one temperature sensor. Each resonator has a resonance frequency in a resonator frequency comb and channels with frequencies in a channel frequency comb are transmitted in the waveguide. Resonance frequencies in the resonator frequency comb are to be adjusted in response to ambient temperature changes detected by the at least one temperature sensors to align the resonance frequency comb with the channel frequency comb.

    摘要翻译： 公开了可调谐谐振器系统和用于调谐谐振器系统的方法。 在一个方面，谐振器系统包括邻近波导设置的谐振器阵列，与谐振器阵列相邻的至少一个温度传感器，以及电连接到至少一个温度传感器的谐振器控制器。 每个谐振器在谐振器频率梳中具有谐振频率，并且在波导中传输具有信道频率梳中的频率的信道。 要响应于由至少一个温度传感器检测到的环境温度变化来调节谐振器频率梳中的谐振频率，以使谐振频率梳与通道频率梳对齐。

    METHODS AND APPARATUS TO DETERMINE AND IMPLEMENT MULTIDIMENSIONAL NETWORK TOPOLOGIES
    13.
    发明申请
    METHODS AND APPARATUS TO DETERMINE AND IMPLEMENT MULTIDIMENSIONAL NETWORK TOPOLOGIES 有权
    确定和实施多维网络拓扑的方法和设备

    公开(公告)号：US20120020242A1

    公开(公告)日：2012-01-26

    申请号：US12841039

    申请日：2010-07-21

    申请人： Moray McLaren ,  Jung Ho Ahn ,  Nathan Lorenzo Binkert ,  Alan Lynn Davis ,  Robert Samuel Schreiber

    发明人： Moray McLaren ,  Jung Ho Ahn ,  Nathan Lorenzo Binkert ,  Alan Lynn Davis ,  Robert Samuel Schreiber

    IPC分类号： H04L12/28

    CPC分类号： H04L41/12

    摘要： Methods and apparatus to determine and implement multidimensional network topologies are disclosed. An example method disclosed herein comprises receiving an input parameter for determining a multidimensional network topology for a network interconnecting a plurality of devices, and determining a set of multidimensional network topologies, each multidimensional network topology of the set comprising a respective plurality of nodes to interconnect the plurality of devices, each node in each multidimensional network topology of the set being fully connected with all neighbor nodes in each dimension of the multidimensional network topology, and each multidimensional network topology of the set satisfying a first constraint based on the input parameter.

    摘要翻译： 公开了确定和实施多维网络拓扑的方法和装置。 本文公开的示例性方法包括接收用于确定用于互连多个设备的网络的多维网络拓扑的输入参数，以及确定一组多维网络拓扑，该集合的每个多维网络拓扑包括相应的多个节点，以将 多个设备，该集合的每个多维网络拓扑中的每个节点与多维网络拓扑的每个维度中的所有相邻节点完全连接，并且该集合的每个多维网络拓扑基于输入参数满足第一约束。

    Three-dimensional memory module architectures
    14.
    发明申请
    Three-dimensional memory module architectures 有权
    三维内存模块架构

    公开(公告)号：US20090103345A1

    公开(公告)日：2009-04-23

    申请号：US11975963

    申请日：2007-10-23

    申请人： Moray McLaren ,  Jung Ho Ahn ,  Alan Lynn Davis ,  Nathan Lorenzo Binkert ,  Norman Paul Jouppi

    发明人： Moray McLaren ,  Jung Ho Ahn ,  Alan Lynn Davis ,  Nathan Lorenzo Binkert ,  Norman Paul Jouppi

    IPC分类号： G11C5/06 ,  G11C13/04

    CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/025 ,  G11C13/04 ,  G11C2211/4016 ,  G11C2213/71 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06534 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    摘要： Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer.

    摘要翻译： 本发明的各种实施例涉及堆叠的存储器模块。 在本发明的一个实施例中，存储器模块包括至少一个堆叠有至少一个存储器层的存储器 - 控制器层。 通过通孔（例如，通过硅通孔）精细地延伸通过堆叠大致垂直于至少一个存储器控制器的表面延伸，从而提供至少一个存储器控制器与至少一个存储器层之间的电子通信。 此外，存储器控制器层包括被配置为向存储器模块传送数据和从存储器模块传送数据的至少一个外部接口。 此外，存储器模块可以包括光学层。 光学层可以被包括在堆叠中并且具有总线波导以将数据传送到至少一个存储器控制器和从至少一个存储器控制器传送数据。 外部接口可以是与光学层接口的光学外部接口。

    PACKET-BASED NETWORKING SYSTEM
    15.
    发明申请
    PACKET-BASED NETWORKING SYSTEM 审中-公开
    基于分组的网络系统

    公开(公告)号：US20110134930A1

    公开(公告)日：2011-06-09

    申请号：US12634224

    申请日：2009-12-09

    申请人： Moray McLaren ,  Alan Lynn Davis

    发明人： Moray McLaren ,  Alan Lynn Davis

    IPC分类号： H04L12/56

    CPC分类号： H04L47/34 ,  H04L1/1614 ,  H04L1/1621 ,  H04L1/1678 ,  H04L1/188 ,  H04L47/19 ,  H04L47/193 ,  H04L69/32 ,  H04L69/324 ,  H04L69/326

    摘要： One embodiment of the present invention is directed to a networking system comprising a sending device, a receiving device, electronic communications components and transmission media through which the sending device and receiving device exchange data packets, and a networking protocol implemented in executable routines, firmware, hardware, or a combination of two or more of executable routines, firmware, hardware that provides for transmission of data in an ordered set of data packets through a sequence established between the sending device and receiving device as a result of transmitting a first data packet from the sending device to the receiving device and returning an acknowledgement by the receiving device to the sending device.

    摘要翻译： 本发明的一个实施例涉及一种网络系统，包括发送设备，接收设备，电子通信组件和传输介质，发送设备和接收设备通过其发送数据分组，以及在可执行例程中实现的网络协议，固件， 硬件或两个或多个可执行例程的组合，固件，硬件，其通过发送设备和接收设备之间建立的序列来提供数据分组的有序集合中的数据的传输，作为从第 所述发送设备发送到所述接收设备并且将所述接收设备的确认返回给所述发送设备。

    STORING CHECKPOINT DATA IN NON-VOLATILE MEMORY
    16.
    发明申请
    STORING CHECKPOINT DATA IN NON-VOLATILE MEMORY 审中-公开
    在非易失性存储器中存储检查点数据

    公开(公告)号：US20110113208A1

    公开(公告)日：2011-05-12

    申请号：US12989981

    申请日：2008-05-01

    申请人： Norman Paul Jouppi ,  Alan Lynn Davis ,  Nidhi Aggarwal ,  Richard Kaufmann

    发明人： Norman Paul Jouppi ,  Alan Lynn Davis ,  Nidhi Aggarwal ,  Richard Kaufmann

    IPC分类号： G06F12/16 ,  G06F13/00

    CPC分类号： G06F11/1438 ,  G06F11/1482 ,  G06F11/203 ,  G06F11/2046

    摘要： Methods and systems for storing checkpoint data in non-volatile memory are described. According to one embodiment, a data storage method includes executing an application using processing circuitry and during the execution, writing data generated by the execution of the application to volatile memory. An indication of a checkpoint is provided after writing the data. After the indication has been provided, the method includes copying the data from the volatile memory to non-volatile memory and, after the copying, continuing the execution of the application. The method may include suspending execution of the application. According to another embodiment, a data storage method includes receiving an indication of a checkpoint associated with execution of one or more applications and, responsive to the receipt, initiating copying of data resulting from execution of the one or more applications from volatile memory to non-volatile memory. In some embodiments, the non-volatile memory may be solid-state non-volatile memory.

    摘要翻译： 描述了用于在非易失性存储器中存储检查点数据的方法和系统。 根据一个实施例，数据存储方法包括使用处理电路执行应用，并且在执行期间，将由应用执行产生的数据写入易失性存储器。 写入数据后提供检查点的指示。 在提供指示之后，该方法包括将数据从易失性存储器复制到非易失性存储器，并且在复制之后继续执行应用程序。 该方法可以包括暂停应用程序的执行。 根据另一个实施例，数据存储方法包括接收与一个或多个应用的​​执行相关联的检查点的指示，并且响应于该接收，开始将由一个或多个应用执行所产生的数据从易失性存储器复制到非易失性存储器， 易失性存储器 在一些实施例中，非易失性存储器可以是固态非易失性存储器。

    Memory interface
    17.
    发明授权
    Memory interface 有权
    内存界面

    公开(公告)号：US09411757B2

    公开(公告)日：2016-08-09

    申请号：US14005196

    申请日：2011-03-14

    申请人： Aniruddha Nagendran Udipi ,  Naveen Muralimanohar ,  Norman Paul Jouppi ,  Rajeev Balasubramonian ,  Alan Lynn Davis

    发明人： Aniruddha Nagendran Udipi ,  Naveen Muralimanohar ,  Norman Paul Jouppi ,  Rajeev Balasubramonian ,  Alan Lynn Davis

    IPC分类号： G06F13/16 ,  G06F13/362 ,  G06F13/38

    CPC分类号： G06F13/3625 ,  G06F13/1605 ,  G06F13/1689

    摘要： The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.

    摘要翻译： 本公开提供了一种用于处理存储器存取操作的方法。 该方法包括至少部分地基于存储器模块的总存储器延迟来确定固定响应时间。 该方法还包括通过数据总线识别从存储器模块接收返回数据的可用时隙，其中当前时钟周期与可用时隙之间的时间差大于或等于固定响应时间。 该方法还包括通过预留可用时隙来创建第一时隙预留。 该方法还包括通过数据总线向存储器模块发出读取请求，其中读取请求以从第一时隙预留时间减去固定响应时间确定的时钟周期发出。

    MEMORY INTERFACE
    19.
    发明申请
    MEMORY INTERFACE 有权
    记忆界面

    公开(公告)号：US20140040518A1

    公开(公告)日：2014-02-06

    申请号：US14005196

    申请日：2011-03-14

    申请人： Aniruddha Nagendran Udipi ,  Naveen Muralimanohar ,  Norman Paul Jouppi ,  Rajeev Balasubramonian ,  Alan Lynn Davis

    发明人： Aniruddha Nagendran Udipi ,  Naveen Muralimanohar ,  Norman Paul Jouppi ,  Rajeev Balasubramonian ,  Alan Lynn Davis

    IPC分类号： G06F13/362

    CPC分类号： G06F13/3625 ,  G06F13/1605 ,  G06F13/1689

    摘要： The present disclosure provides a method for processing memory access operations. The method includes determining a fixed response time based at least in part, on a total memory latency of a memory module. The method also includes identifying an available time slot for receiving return data from the memory module over a data bus, wherein the time difference between a current clock cycle and the available time slot is greater than or equal to the fixed response time. The method also includes creating a first slot reservation by reserving the available time slot. The method also includes issuing as read request to the memory module over the data bus, wherein the read request is issued at a clock cycle determined by subtracting the fixed response time from a time of the first slot reservation.

    摘要翻译： 本公开提供了一种用于处理存储器存取操作的方法。 该方法包括至少部分地基于存储器模块的总存储器延迟来确定固定响应时间。 该方法还包括通过数据总线识别从存储器模块接收返回数据的可用时隙，其中当前时钟周期与可用时隙之间的时间差大于或等于固定响应时间。 该方法还包括通过预留可用时隙来创建第一时隙预留。 该方法还包括通过数据总线向存储器模块发出读取请求，其中读取请求以从第一时隙预留时间减去固定响应时间确定的时钟周期发出。