公开(公告)号：US06812540B2

公开(公告)日：2004-11-02

申请号：US10298682

申请日：2002-11-19

申请人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Riichiro Takemura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Hisao Asakura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L2900

CPC分类号： H01L27/105 ,  H01L27/10897

摘要： A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4−L5), (L6−L5), and (L4−L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.

摘要翻译： 提供了一种半导体集成电路器件，其中可以减小MISFET的阈值电压的变化，例如构成读出放大器的MISFET对的变化。 在形成驱动存储单元所需的诸如读出放大器电路的逻辑电路的逻辑电路区域中，没有栅电极的n型有源区域被布置在有效区域的两个边缘上，p沟道MISFET对 用于构成读出放大器。 假设有源区域nwp1和nw1之间的宽度为L4，有效区域nwp2和nw2之间的宽度为L6，有效区域nwp1和nwp2之间的宽度为L5（L4-L5），（L6-L5）和（ L4-L6）设定为几乎为零或小于最小加工尺寸的两倍，使得可以减小宽度L4，L5和L6的器件隔离沟槽形状的变化，并且可以减小阈值电压差 可以减少MISFET对。

公开(公告)号：US06809364B2

公开(公告)日：2004-10-26

申请号：US10630695

申请日：2003-07-31

申请人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

公开(公告)号：US06621110B1

公开(公告)日：2003-09-16

申请号：US09592648

申请日：2000-06-13

申请人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Hideyuki Matsuoka ,  Satoru Yamada ,  Isamu Asano ,  Ryo Nagai ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H01L27108

CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  Y10S257/906 ,  Y10S257/907 ,  Y10S257/908

摘要： A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.

摘要翻译： 开放位线结构的DRAM具有小于折叠位线结构的DRAM的单元面积，并且易受噪声影响。 开放位线结构的常规DRAM具有大的位线电容，并且易于噪声或具有大的单元面积。 已经没有开放位线结构的DRAM具有小的位线电容，不能被噪声感知并且具有小的单元面积。 本发明形成与位线不对齐的电容器下电极插孔，以减少位线电容。 位线形成为小的宽度，电容器下电极插头从与位线相对应的位置的位置脱位，并且触点形成为减小的直径，以避免增加电池面积。 因此，提供了耐噪声且具有小单元面积的开放位线结构的半导体存储装置。

公开(公告)号：US20120241715A1

公开(公告)日：2012-09-27

申请号：US13493442

申请日：2012-06-11

申请人： YUICHI MATSUI ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

发明人： YUICHI MATSUI ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

IPC分类号： H01L27/26 ,  H01L47/00

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

公开(公告)号：US20090250680A1

公开(公告)日：2009-10-08

申请号：US12487492

申请日：2009-06-18

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Kenzo Kurotsuchi ,  Tsuyoshi Yamauchi

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Motoyasu Terao ,  Kenzo Kurotsuchi ,  Tsuyoshi Yamauchi

IPC分类号： H01L47/00

CPC分类号： H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16

摘要： With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.

摘要翻译： 通过高速非易失性相变存储器，提高了刷新次数的可靠性。 在使用MISFET作为选择存储单元的晶体管的相变存储器的存储单元形成区域中，形成了使用相变材料的包括电阻元件的存储单元的相变材料层，用于常用。 结果，减少了通过蚀刻对存储单元元件的隔离而导致的相变材料的形状变化和组成变化，从而提高了存储单元的刷新次数的可靠性。

公开(公告)号：US07335907B2

公开(公告)日：2008-02-26

申请号：US10790881

申请日：2004-03-03

申请人： Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Hideyuki Matsuoka ,  Tsuyoshi Yamauchi

发明人： Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Hideyuki Matsuoka ,  Tsuyoshi Yamauchi

IPC分类号： H01L47/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1213 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1625

摘要： A phase change memory device is provided which is constituted by memory cells using memory elements and select transistors and having high heat resistance to be capable of an operation at 140 degrees or higher. As a device configuration, a recording layer of which, of Zn—Ge—Te, content of Zn, Cd or the like is 20 atom percent or more, content of at least one element selected from the group consisting of Ge and Sb is less than 40 atom percent, and content of Te is 40 atom percent or more is used. It is thereby possible to implement the memory device usable for an application which may be performed at a high temperature such as an in-vehicle use.

摘要翻译： 提供一种相变存储器件，其由使用存储元件和选择晶体管的存储器单元构成，并且具有高耐热性能够在140度以上的操作。 作为器件结构，其中Zn-Ge-Te，Zn，Cd等的含量为20原子％以上的记录层选自Ge和Sb中的至少一种元素的含量较少 40原子％以上，Te含量为40原子％以上。 由此，可以实现可以在诸如车载用途的高温下执行的应用的存储装置。

公开(公告)号：US20070170413A1

公开(公告)日：2007-07-26

申请号：US11596220

申请日：2005-05-09

申请人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

发明人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

IPC分类号： H01L29/04

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

摘要翻译： 由于这种材料对高熔点金属和氧化硅膜具有低粘附性，所以相变存储器的制造过程已经受到硫属化物材料易于分层的问题的困扰。 此外，硫族化物材料具有低的热稳定性，因此在相变存储器的制造过程中倾向于升华。 根据本发明，在硫族化物材料层上和下方形成导电或绝缘粘合剂层以增强其分层强度。 此外，在硫族化物材料层的侧壁上形成由氮化物膜构成的保护膜，以防止硫属化物材料层的升华。

公开(公告)号：US06900492B2

公开(公告)日：2005-05-31

申请号：US10164008

申请日：2002-06-07

申请人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

发明人： Norikatsu Takaura ,  Hideyuki Matsuoka ,  Shinichiro Kimura ,  Ryo Nagai ,  Satoru Yamada

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/49 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10894 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823857 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10888 ,  H01L27/10897 ,  H01L27/11502 ,  H01L27/11507 ,  H01L29/4941 ,  H01L29/6656

摘要： A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved.Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

摘要翻译： DRAM存储单元的刷新特性得到改善，并且在周边形成的构成逻辑电路的MISFET的性能得到改善。 存储单元区域中的每个栅电极由p型多晶硅形成，并且每个栅电极上的帽绝缘膜和其侧壁上的侧壁膜由氧化硅膜形成。 通过CMP方法对形成在栅电极和栅电极之间的多晶硅膜进行抛光，形成接触电极。 此外，在逻辑电路区域中的栅电极的侧壁上形成各自由氧化硅膜和多晶硅膜的叠层膜构成的侧壁膜，并且将这些膜用作掩模以形成半导体区域。 结果，可以以自对准的方式降低硼渗透并形成接触电极。 此外，可以提高构成逻辑电路的MISFET的性能。

公开(公告)号：US08890107B2

公开(公告)日：2014-11-18

申请号：US12613235

申请日：2009-11-05

申请人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

发明人： Yuichi Matsui ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Naoki Yamamoto ,  Hideyuki Matsuoka ,  Tomio Iwasaki

IPC分类号： H01L29/04 ,  H01L27/24 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.

摘要翻译： 由于这种材料对高熔点金属和氧化硅膜具有低粘附性，所以相变存储器的制造过程已经受到硫属化物材料易于分层的问题的困扰。 此外，硫族化物材料具有低的热稳定性，因此在相变存储器的制造过程中倾向于升华。 根据本发明，在硫族化物材料层上和下方形成导电或绝缘粘合剂层以增强其分层强度。 此外，在硫族化物材料层的侧壁上形成由氮化物膜构成的保护膜，以防止硫属化物材料层的升华。

公开(公告)号：US20050128799A1

公开(公告)日：2005-06-16

申请号：US11002245

申请日：2004-12-03

申请人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka

发明人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Osamu Tonomura ,  Motoyasu Terao ,  Hideyuki Matsuoka

IPC分类号： G11C13/00 ,  G11C11/00 ,  G11C13/02 ,  G11C16/02 ,  G11C17/00 ,  H01L27/10

CPC分类号： G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2013/009 ,  G11C2213/76 ,  G11C2213/79

摘要： In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. At this time, if a constant voltage source is used, not only the phase change portion assumes a state of a low resistance, but also a large current flows, so that a sample concerned is overheated and goes into a state of a high resistance. Thus, it is difficult to make the phase change portion low in resistance stably. When the gate voltage of a memory cell selection transistor QM is controlled with MISFET to afford a low resistance state, the maximum amount of current applied to the sample is limited by the application of a medium-state voltage.

摘要翻译： 在非易失性相变存储器中，利用相变部分的电阻变化来记录信息。 当相变部分产生焦耳热并保持在特定温度时，其进入低电阻状态。 此时，如果使用恒定电压源，则不仅相变部分呈现低电阻状态，而且流过大电流，使得有关样品过热并进入高电阻状态。 因此，难以稳定地使相位变化部的电阻低。 当用MISFET控制存储单元选择晶体管QM的栅极电压以提供低电阻状态时，施加到样品的最大电流量受到施加中等电压的限制。