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公开(公告)号：US20210177241A1
公开(公告)日：2021-06-17
申请号：US17189773
申请日：2021-03-02
Applicant: OLYMPUS CORPORATION
Inventor： Takanori Tanaka , Masato Osawa
Abstract: In an imaging system, an image transmission circuit is configured to output image data to a signal line in a first mode. A signal reception circuit is configured to receive a clock control signal for adjusting a frequency of a camera clock from an image reception unit in a second mode. A signal output circuit is configured to output a first electric potential and the clock control signal to the signal line. The first electric potential corresponds to a signal level that is not included in a range of a signal level of the image data output to the signal line. A communication control circuit is configured to switch communication modes from the first mode to the second mode when the communication control circuit detects the first electric potential in the first mode.
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公开(公告)号：US20190020841A1
公开(公告)日：2019-01-17
申请号：US16126092
申请日：2018-09-10
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
IPC: H04N5/3745 , H03M1/46
Abstract: An AD converter includes a first DAC circuit, a second DAC circuit, a comparison circuit, a control circuit, and a control switch. The comparison circuit is connected to a first output node of the first DAC circuit and a second output node of the second DAC circuit and compares an electric potential of the first output node with an electric potential of the second output node. The control circuit controls the first DAC circuit and the second DAC circuit in accordance with a result of the comparison acquired by the comparison circuit. The control switch controls turning on and off of connection between a first input node of the first DAC circuit and a second input node of the second DAC circuit.
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公开(公告)号：US20180331688A1
公开(公告)日：2018-11-15
申请号：US16043920
申请日：2018-07-24
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Shuzo Hiraide , Masato Osawa , Hideki Kato
IPC: H03M1/00
CPC classification number: H03M1/002 , H03M1/00 , H03M1/001 , H03M1/10 , H03M1/12 , H03M1/38 , H03M1/74
Abstract: A successive approximation type A/D conversion circuit includes a first capacitor circuit, a second capacitor circuit, a plurality of comparison circuits, a determination circuit, and a control circuit. The determination circuit counts a first number of first state and a second number of second state with respect to a plurality of first digital signals output from the plurality of comparison circuits. The determination circuit outputs a control signal for stopping the plurality of comparison circuits to the control circuit when an absolute value of a difference between the first number and the second number is equal to or smaller than 1. The control circuit stops the plurality of comparison circuits on the basis of the control signal.
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公开(公告)号：US10057514B2
公开(公告)日：2018-08-21
申请号：US15297685
申请日：2016-10-19
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
CPC classification number: H04N5/341 , H04N5/3692 , H04N5/3698 , H04N5/37457 , H04N5/376 , H04N5/3765 , H04N5/378
Abstract: An image sensor includes n light receiving elements including first to n-th light receiving elements, each of the light receiving elements generating photoelectric conversion signals, n sequencers including first to n-th sequencers, each of the sequencers having both a sequencer input terminal to which a k-th horizontal control signal is input, and a sequencer output terminal from which a (k+1)-th horizontal control signal is output, and n switches including first to n-th switches, each of the switches having a switch input terminal to which a signal corresponding to the photoelectric conversion signal is input, a switch control terminal to which a k-th pixel control signal is input, and a switch output terminal which is electrically connected to the switch input terminal, wherein n is a natural number of 2 or more, and k is a natural number of 1 to n.
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公开(公告)号：US11856308B2
公开(公告)日：2023-12-26
申请号：US17420775
申请日：2019-01-09
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
CPC classification number: H04N25/745 , A61B1/00006 , A61B1/00009 , A61B1/00013 , A61B1/00117 , H04N25/75
Abstract: An image sensor includes: a pixel unit including pixels configured to generate a first signal corresponding to an amount of received light, and output the first signal; an AD converter configured to convert the first signal into a digital second signal by performing AD conversion processing for the first signal, and output the second signal; a transmitter/receiver configured to transmit and receive, in a time division manner, transmission data including at least the second signal in a first period, and reception data input from an outside in a second period; and a first generator configured to generate a first clock signal synchronized with the clock edge included in the reception data. The transmitter/receiver is configured to switch between the first period and the second period every horizontal line in the pixel unit, and transmit and receive the transmission data and the reception data in a time division manner.
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Patent Agency Ranking
公开(公告)号：US20210195144A1
公开(公告)日：2021-06-24
申请号：US17190778
申请日：2021-03-03
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
IPC: H04N7/18
Abstract: In an imaging system according to an embodiment of the present invention, a camera unit is configured to transmit imaging data to an information-processing unit as a downlink packet. The camera unit is configured to hold predetermined data in the imaging data as a transmission key. The information-processing unit is configured to receive the downlink packet, recognize the predetermined data in the imaging data as the transmission key, and generate a reception key on the basis of the transmission key. The information-processing unit is configured to transmit an uplink packet including the reception key and a register-setting signal indicating an imaging condition to the camera unit. The camera unit is configured to write the register-setting signal received with the reception key in a register when the transmission key and the reception key meet a predetermined condition.
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公开(公告)号：US10812099B2
公开(公告)日：2020-10-20
申请号：US16106687
申请日：2018-08-21
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Shuzo Hiraide , Masato Osawa
Abstract: In an AD converter, a first capacitor DAC circuit performs a first operation in parallel with a second operation by a second capacitor DAC circuit, and the first capacitor DAC circuit performs the second operation in parallel with the first operation by the second capacitor DAC circuit. Electric charge corresponding to an input signal is sampled in the first operation. AD conversions are sequentially performed on the basis of the electric charge sampled in each first capacitor included in a plurality of first capacitors or each second capacitor included in a plurality of second capacitors in the second operation. The first capacitor DAC circuit and the second capacitor DAC circuit alternately perform the first operation and the second operation.
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公开(公告)号：US10757357B2
公开(公告)日：2020-08-25
申请号：US16442666
申请日：2019-06-17
Applicant: OLYMPUS CORPORATION
Inventor： Yasunari Harada , Shuzo Hiraide , Masato Osawa , Satoru Adachi
Abstract: An imaging element includes: a plurality of pixels where each pixel is configured to generate an imaging signal; a noise eliminating circuit configured to eliminate a noise component included in the imaging signal; a plurality of column source follower buffers where each column source follower buffer is configured to amplify the imaging signal from which the noise component has been eliminated by the noise eliminating circuit, and output the amplified signal; a horizontal scanning circuit configured to sequentially select the column source follower buffer and output the imaging signal; and a buffer circuit which is connected with the column source follower buffer sequentially selected by the horizontal scanning circuit to form a voltage follower circuit, the buffer circuit being configured to perform impedance conversion on a voltage of the imaging signal output from the column source follower buffer, and output the converted signal to an outside.
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公开(公告)号：US10729311B2
公开(公告)日：2020-08-04
申请号：US16445373
申请日：2019-06-19
Applicant: OLYMPUS CORPORATION
Inventor： Masato Osawa
Abstract: A signal processing system includes: a transmission channel; a common-mode signal transmitting circuit configured to output an uplink signal to the transmission channel in a common mode; a common-mode signal detecting circuit configured to detect a common-mode signal from the uplink signal transmitted by the transmission channel; a downlink reference clock signal generating circuit configured to generate a downlink reference clock signal at a second frequency with reference to the first clock edge of the common-mode signal detected by the common-mode signal detecting circuit; a downlink data generating circuit configured to generate downlink data; a differential signal transmitting circuit configured to output, as a downlink signal, the downlink data generated by the downlink data generating circuit to the transmission channel in a differential mode; and a differential signal receiving circuit configured to extract a differential signal from the downlink signal.
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公开(公告)号：US10277845B2
公开(公告)日：2019-04-30
申请号：US15902014
申请日：2018-02-22
Applicant: OLYMPUS CORPORATION
Inventor： Hideki Kato , Yasunari Harada , Masato Osawa
Abstract: There is provided a method of driving a solid-state imaging device, the solid-state imaging device including a plurality of column circuits which are arranged for each column of pixels and an amplification and selection circuit configured to amplify a differential signal based on a column pixel signal and a column reset signal, the method including causing the amplification and selection circuit to perform at least two operations among a first operation of sampling the column pixel signal, a second operation of sampling the column reset signal, and a third operation of output the amplified differential signal in parallel in the same period; and causing components connected to different horizontal signal lines to perform operations corresponding to the first to third operation in that order, and causing the components to perform different operations in parallel in the same period with respect to the first to third operations.
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