公开(公告)号：US11844496B2

公开(公告)日：2023-12-19

申请号：US17189773

申请日：2021-03-02

Applicant: OLYMPUS CORPORATION

Inventor： Takanori Tanaka ,  Masato Osawa

IPC: A61B1/00 ,  A61B1/045 ,  H04N7/18 ,  H04N23/60

CPC classification number: A61B1/00006 ,  A61B1/00009 ,  A61B1/00013 ,  A61B1/045 ,  H04N7/18 ,  H04N23/60

Abstract: In an imaging system, an image transmission circuit is configured to output image data to a signal line in a first mode. A signal reception circuit is configured to receive a clock control signal for adjusting a frequency of a camera clock from an image reception unit in a second mode. A signal output circuit is configured to output a first electric potential and the clock control signal to the signal line. The first electric potential corresponds to a signal level that is not included in a range of a signal level of the image data output to the signal line. A communication control circuit is configured to switch communication modes from the first mode to the second mode when the communication control circuit detects the first electric potential in the first mode.

公开(公告)号：US20150326241A1

公开(公告)日：2015-11-12

申请号：US14676414

申请日：2015-04-01

Applicant: OLYMPUS CORPORATION

Inventor： Takanori Tanaka

IPC: H03M1/34 ,  H04N5/378

CPC classification number: H03M1/34 ,  H03M1/123 ,  H03M1/145 ,  H03M1/50 ,  H03M1/56 ,  H04N5/378

Abstract: An analog-to-digital (AD) converter has a latch section having latch units, a capacitor, and a latch control signal line connected to the latch units. A third voltage less than a first voltage and greater than a second voltage is applied as a power supply voltage to the latch units. When the capacitor is electrically connected to the latch control signal line, a potential of the latch control signal line becomes greater than or equal to the third voltage. Only when the electrical connection between the capacitor and the latch control signal line is disconnected, the first voltage is applied to the capacitor and the second voltage is applied to the latch control signal line. When the potential of the latch control signal line becomes greater than or equal to the third voltage, the latch units latch clock signals.

Abstract translation: 模数（AD）转换器具有锁存单元，具有锁存单元，电容器和连接到锁存单元的锁存控制信号线。 施加小于第一电压且大于第二电压的第三电压作为电源电压施加到锁存单元。 当电容器电连接到锁存控制信号线时，锁存控制信号线的电位变得大于或等于第三电压。 只有当电容器和锁存器控制信号线之间的电连接断开时，第一个电压被施加到电容器，第二个电压被施加到锁存控制信号线。 当锁存控制信号线的电位变得大于或等于第三电压时，锁存单元锁存时钟信号。

公开(公告)号：US09035227B2

公开(公告)日：2015-05-19

申请号：US13662596

申请日：2012-10-29

Applicant: OLYMPUS CORPORATION

Inventor： Takanori Tanaka ,  Susumu Yamazaki

IPC: H01L27/00 ,  H04N5/335 ,  H03M1/34 ,  H04N5/376 ,  H03M1/50 ,  H03M1/12 ,  H04N5/378

CPC classification number: H04N5/3765 ,  H03M1/123 ,  H03M1/502 ,  H04N5/378

Abstract: In this solid-state imaging device, an output signal of any one of a plurality of delay units that output signals of logic states in accordance with a level of a pixel signal is input to an input terminal of a latch circuit that latches a logic state of the output signal. A NAND circuit and an INV circuit stop until a control signal output timing at which a control signal in accordance with the level of the pixel signal is output, and operate after the control signal output timing. A switch circuit outputs the output signal of the one of the plurality of delay units through a signal line from an output terminal until the control signal output timing, and switches a connection at a latch timing after a predetermined time elapses from the control signal output timing such that the NAND circuit and the INV circuit latch the logic state of the output signal of the one of the plurality of delay units.

Abstract translation: 在该固态成像装置中，将根据像素信号的电平输出逻辑状态的信号的多个延迟单元中的任一个的输出信号输入到锁存逻辑状态的锁存电路的输入端子 的输出信号。 NAND电路和INV电路停止，直到输出根据像素信号的电平的控制信号的控制信号输出定时，并且在控制信号输出定时之后操作。 开关电路通过信号线从输出端子输出多个延迟单元中的一个延迟单元的输出信号，直到控制信号输出定时，并且在从控制信号输出定时经过预定时间之后的锁存定时处切换连接 使得NAND电路和INV电路锁存多个延迟单元之一的输出信号的逻辑状态。

公开(公告)号：US20130299676A1

公开(公告)日：2013-11-14

申请号：US13887939

申请日：2013-05-06

Applicant: OLYMPUS CORPORATION

Inventor： Takanori Tanaka

IPC: H03M1/34 ,  H04N5/335

CPC classification number: H03M1/34 ,  H03M1/123 ,  H03M1/56 ,  H04N5/3355 ,  H04N5/378

Abstract: An A/D conversion circuit and a solid-state imaging device are able to reduce current consumption, and two input terminals of a NAND element included in a latch circuit receive a corresponding one of a plurality of clock signals and an enable signal. The enable signal is not input to the NAND element before an end timing of A/D conversion, and is input to the NAND element at the end timing of the A/D conversion and at a timing at which latching is performed. The latch circuit latches no clock signal when the enable signal is not input.

Abstract translation: A / D转换电路和固态成像装置能够减少电流消耗，并且包含在锁存电路中的NAND元件的两个输入端子接收多个时钟信号和使能信号中相应的一个。 在A / D转换的结束定时之前，使能信号不被输入到NAND元件，并且在A / D转换的结束时刻和在执行锁存的定时输入到NAND元件。 当使能信号未输入时，锁存电路不锁存时钟信号。

公开(公告)号：US20220407501A1

公开(公告)日：2022-12-22

申请号：US17893832

申请日：2022-08-23

Applicant: OLYMPUS CORPORATION

Inventor： Takanori Tanaka ,  Shuzo Hiraide

IPC: H03H11/16 ,  H03L7/081

Abstract: In a phase adjustment circuit, a binary circuit is configured to output a binary signal on the basis of an edge of a video signal. A phase-delayed clock signal generation circuit is configured to generate a phase-delayed clock signal having a later phase than a phase of a clock signal by a first delay amount. A delay time control circuit is configured to cause a phase of the binary signal and the phase of the phase-delayed clock signal to match each other by adjusting the first delay amount. A sampling signal generation circuit is configured to generate a sampling signal having a later phase than the phase of the clock signal by a second delay amount. The second delay amount is in accordance with both a phase shift amount, which is based on the clock signal, and the first delay amount.

公开(公告)号：US10456023B2

公开(公告)日：2019-10-29

申请号：US15940089

申请日：2018-03-29

Applicant: OLYMPUS CORPORATION

Inventor： Nana Akahane ,  Satoru Adachi ,  Takanori Tanaka

IPC: A61B1/05 ,  A61B1/04 ,  H04N5/3745 ,  H04N5/378 ,  H04N7/18 ,  A61B1/00 ,  A61B1/045 ,  H04N5/225 ,  H04N5/357 ,  H04N5/232 ,  H04N5/345

Abstract: An image sensor includes: pixels; first transfer lines configured to transfer imaging signals of shared pixels that are present in a plurality of different rows and share a single column transfer line for each predetermined number of pixels adjacent in a row direction and; a constant current source configured to transfer the imaging signals; output units configured to externally output the imaging signals; and a control unit configured to simultaneously and externally outputs, by simultaneously driving the plurality of shared pixels present in a same single column transfer line in the plurality of different rows, each of the plurality of imaging signals, which are output from the shared pixels and are present in the same column in the plurality of different rows, and externally output all of the imaging signals of the shared pixels present in the plurality of different rows same number of times as the predetermined number.

公开(公告)号：US09166613B2

公开(公告)日：2015-10-20

申请号：US13887939

申请日：2013-05-06

Applicant: OLYMPUS CORPORATION

Inventor： Takanori Tanaka

IPC: H03M1/56 ,  H03M1/34 ,  H04N5/335 ,  H04N5/378 ,  H03M1/12

CPC classification number: H03M1/34 ,  H03M1/123 ,  H03M1/56 ,  H04N5/3355 ,  H04N5/378

Abstract: An A/D conversion circuit and a solid-state imaging device are able to reduce current consumption, and two input terminals of a NAND element included in a latch circuit receive a corresponding one of a plurality of clock signals and an enable signal. The enable signal is not input to the NAND element before an end timing of A/D conversion, and is input to the NAND element at the end timing of the A/D conversion and at a timing at which latching is performed. The latch circuit latches no clock signal when the enable signal is not input.

Abstract translation: A / D转换电路和固态成像装置能够减少电流消耗，并且包含在锁存电路中的NAND元件的两个输入端子接收多个时钟信号和使能信号中相应的一个。 在A / D转换的结束定时之前，使能信号不被输入到NAND元件，并且在A / D转换的结束时刻和在执行锁存的定时输入到NAND元件。 当使能信号未输入时，锁存电路不锁存时钟信号。

公开(公告)号：US10542226B2

公开(公告)日：2020-01-21

申请号：US16152629

申请日：2018-10-05

Applicant: OLYMPUS CORPORATION

Inventor： Takanori Tanaka ,  Masashi Saito ,  Takatoshi Igarashi ,  Satoru Adachi ,  Katsumi Hosogai ,  Nana Akahane

IPC: H04N5/345 ,  H04N5/369 ,  H04N5/378 ,  A61B1/00 ,  A61B1/045 ,  A61B1/05 ,  H01L27/146 ,  H04N5/376

Abstract: An imaging element includes: a pixel chip where a pixel unit and a vertical selecting unit are arranged, the pixel unit including plural pixels that are arranged in a two-dimensional matrix, the pixels being configured to generate and output imaging signals; a transmission chip where at least a power source unit and a transmission unit are arranged; plural capacitative chips, each capacitative chip having capacitance functioning as a bypass condenser for a power source in the power source unit; and plural connecting portions configured to electrically connect the pixel chip, the transmission chip, and the capacitative chip respectively to another chip. The transmission chip is layered and connected at a back surface side of the pixel chip. The capacitative chips are layered and connected at a back surface side of the transmission chip. The connecting portions are arranged so as to overlap one another.

公开(公告)号：US10456022B2

公开(公告)日：2019-10-29

申请号：US15939740

申请日：2018-03-29

Applicant: OLYMPUS CORPORATION

Inventor： Takatoshi Igarashi ,  Noriyuki Fujimori ,  Makoto Ono ,  Masashi Saito ,  Satoru Adachi ,  Nana Akahane ,  Takanori Tanaka ,  Katsumi Hosogai

IPC: A61B1/05 ,  H01L25/065 ,  H01L25/07 ,  H01L25/16 ,  H01L25/18 ,  H01L27/14 ,  H01L27/146 ,  H04N5/378 ,  A61B1/00 ,  A61B1/045 ,  A61B1/06 ,  H01L21/66 ,  H04N5/345 ,  H04N5/376 ,  H04N7/10 ,  H04N5/225 ,  H04N5/232 ,  H04N5/369

Abstract: An imaging device includes: a first chip including a light receiving unit, and a read circuit; a second chip including a timing control circuit, an A/D conversion circuit, and a cable transmission circuit; and a connection unit configured to connect the first and the second chips. The read circuit includes a column read circuit and a horizontal selection circuit, and a vertical selection circuit. The connection unit of the first chip is provided in a first area along a side of the rectangular light receiving unit, and in a second area adjacent to the column read circuit, the horizontal selection circuit, and the vertical selection circuit. The connection unit of the second chip is provided in a third area around the timing control circuit, the A/D conversion circuit, and the cable transmission circuit and in a fourth area adjacent to the timing control circuit and the A/D conversion circuit.

公开(公告)号：US20160057370A1

公开(公告)日：2016-02-25

申请号：US14933658

申请日：2015-11-05

Applicant: OLYMPUS CORPORATION

Inventor： Takanori Tanaka

IPC: H04N5/378 ,  H04N5/63 ,  H04N5/376

CPC classification number: H04N5/378 ,  H01L27/14636 ,  H04N5/3765 ,  H04N5/63

Abstract: A solid-state imaging device includes a pixel unit, a reference signal generation unit including current sources, and analog-to-digital (A/D) conversion units. The A/D conversion units include comparators and counters. Each of the A/D conversion units includes at least one of the comparators and at least one of the counters which are lined up in a column direction of the pixel unit. The current sources are lined up in a row direction of the pixel unit, and face the comparators of the A/D conversion units in the column direction of the pixel unit. The comparators of the A/D conversion units are arranged between the current sources and the counters of the A/D conversion units.

Abstract translation: 固态成像装置包括像素单元，包括电流源的参考信号生成单元和模数（A / D）转换单元。 A / D转换单元包括比较器和计数器。 每个A / D转换单元包括至少一个比较器和至少一个在像素单元的列方向排列的计数器。 电流源沿像素单元的行方向排列，并且与像素单元的列方向上的A / D转换单元的比较器相对。 A / D转换单元的比较器布置在电流源和A / D转换单元的计数器之间。