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公开(公告)号：US20160313996A1
公开(公告)日：2016-10-27
申请号：US15086711
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
Abstract: A computer processor with an address register file is disclosed. The computer processor may include a memory. The computer processor may further include a general purpose register file comprising at least one general purpose register. The computer processor may further include an address register file comprising at least one address register. The computer processor may further include having access to the memory, the general purpose register file, and the address register file. The processing logic may execute a memory access instruction that accesses one or more memory locations in the memory at one or more corresponding addresses computed by retrieving the value of an address register of the at least one register of the address register file specified in the instruction and adding a displacement value encoded in the instruction.
Abstract translation: 公开了一种具有地址寄存器文件的计算机处理器。 计算机处理器可以包括存储器。 计算机处理器还可以包括包括至少一个通用寄存器的通用寄存器文件。 计算机处理器还可以包括包括至少一个地址寄存器的地址寄存器文件。 计算机处理器还可以包括访问存储器，通用寄存器文件和地址寄存器文件。 处理逻辑可以执行存储器访问指令，该存储器访问指令通过检索指令中指定的地址寄存器文件的至少一个寄存器的地址寄存器的值而计算的一个或多个对应地址访问存储器中的一个或多个存储器位置，以及 添加在指令中编码的位移值。
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公开(公告)号：US20160313995A1
公开(公告)日：2016-10-27
申请号：US15086752
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC: G06F9/30
CPC classification number: G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F12/1027 , G06F2212/452 , G06F2212/60 , G06F2212/602 , G06F2212/6028 , G06F2212/651 , G06F2212/684
Abstract: A computer processor with indirect only branching is disclosed. The computer processor may include one or more target registers. The computer processor may include processing logic in signal communication with the one or more target registers. The processing logic may execute a non-interrupting branch instruction based on a value stored in a target register of the one or more target registers. The non-interrupting branch instruction may use the one or more target registers to specify a destination address of a branch specified by the non-interrupting branch instruction.
Abstract translation: 公开了一种仅间接分支的计算机处理器。 计算机处理器可以包括一个或多个目标寄存器。 计算机处理器可以包括与一个或多个目标寄存器进行信号通信的处理逻辑。 处理逻辑可以基于存储在一个或多个目标寄存器的目标寄存器中的值来执行非中断分支指令。 非中断分支指令可以使用一个或多个目标寄存器来指定由非中断分支指令指定的分支的目的地地址。
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13.发明申请METHOD AND APPARATUS FOR ENABLING A PROCESSOR TO GENERATE PIPELINE CONTROL SIGNALS 有权使用处理器生成管道控制信号的方法和装置公开(公告)号：US20150220342A1
公开(公告)日：2015-08-06
申请号：US14539104
申请日：2014-11-12
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： C. John Glossner , Gary J. Nacer , Murugappan Senthilvelan , Vitaly Kalashnikov , Arthur J. Hoane , Paul D'Arcy , Sabin D. Iancu , Shenghong Wang
CPC classification number: G06F9/3822 , G06F9/3836 , G06F9/3853
Abstract: A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.
Abstract translation: 计算机处理器的链接位解码器接收指令流。 链接位解码器从指令流中选择一组指令。 链接位解码器从指令流的每个指令中提取指定的位以产生一系列链接位。 链接位解码器解码链接序列。 考虑到解码的链接序列，链接位解码器识别所选择的指令组之中的零个或多个指令流相关性。 链接位解码器输出控制信号以使得处理器的一个或多个管线级鉴于所述组指令序列中所识别的零个或多个指令流依赖性来执行所选择的指令组。
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14.发明授权公开(公告)号：US11544214B2
公开(公告)日：2023-01-03
申请号：US14709730
申请日：2015-05-12
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola , Vitaly Kalashnikov , Sitij Agrawal
Abstract: A computer processor comprising a vector unit is disclosed. The vector unit may comprise a vector register file comprising at least one register to hold a varying number of elements. The vector unit may further comprise a vector length register file comprising at least one register to specify the number of operations of a vector instruction to be performed on the varying number of elements in the at least one register of the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
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公开(公告)号：US10908909B2
公开(公告)日：2021-02-02
申请号：US15155570
申请日：2016-05-16
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan
Abstract: A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include switching mode logic to switch between the first mode and the second mode.
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Patent Agency Ranking
公开(公告)号：US10514915B2
公开(公告)日：2019-12-24
申请号：US15086711
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC: G06F9/30 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F9/32 , G06F9/355 , G06F12/0862 , G06F12/1027 , G06F3/06
Abstract: A computer processor with an address register file is disclosed. The computer processor may include a memory. The computer processor may further include a general purpose register file comprising at least one general purpose register. The computer processor may further include an address register file comprising at least one address register. The computer processor may further include having access to the memory, the general purpose register file, and the address register file. The processing logic may execute a memory access instruction that accesses one or more memory locations in the memory at one or more corresponding addresses computed by retrieving the value of an address register of the at least one register of the address register file specified in the instruction and adding a displacement value encoded in the instruction.
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公开(公告)号：US10339095B2
公开(公告)日：2019-07-02
申请号：US14716285
申请日：2015-05-19
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola , Vitaly Kalashnikov , Sitij Agrawal
Abstract: A computer processor is disclosed. The computer processor comprises a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor further comprises processing logic configured to operate on the varying number of elements in the vector register file using one or more digital signal processing instructions. The computer processor may be implemented as a monolithic integrated circuit.
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18.发明授权公开(公告)号：US10339094B2
公开(公告)日：2019-07-02
申请号：US14716216
申请日：2015-05-19
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary J. Nacer , C. John Glossner , Arthur Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola , Vitaly Kalashnikov , Sitij Agrawal
Abstract: A computer processor is disclosed. The computer processor comprises one or more processor resources. The computer processor further comprises a plurality of hardware thread units coupled to the one or more processor resources. The computer processor may be configured to permit simultaneous access to the one or more processor resources by only a subset of hardware thread units of the plurality of hardware thread units. The number of hardware threads in the subset may be less than the total number of hardware threads of the plurality of hardware thread units.
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19.发明授权公开(公告)号：US09792116B2
公开(公告)日：2017-10-17
申请号：US15087204
申请日：2016-03-31
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： Mayan Moudgill , Gary Nacer , C. John Glossner , A. Joseph Hoane , Paul Hurtley , Murugappan Senthilvelan , Pablo Balzola
IPC: G06F12/10 , G06F9/30 , G06F3/06 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F12/0862 , G06F9/32 , G06F9/355
CPC classification number: G06F9/30029 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G06F9/30 , G06F9/30032 , G06F9/30043 , G06F9/30047 , G06F9/30054 , G06F9/30058 , G06F9/3013 , G06F9/322 , G06F9/355 , G06F12/0862 , G06F12/0875 , G06F12/0893 , G06F12/1009 , G06F2212/452 , G06F2212/60 , G06F2212/602
Abstract: A computer processor that implements pre-translation of virtual addresses with target registers is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual instruction address, the virtual instruction address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.
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公开(公告)号：US09558000B2
公开(公告)日：2017-01-31
申请号：US14539342
申请日：2014-11-12
Applicant: Optimum Semiconductor Technologies, Inc.
Inventor： C. John Glossner , Gary J. Nacer , Murugappan Senthilvelan , Vitaly Kalashnikov , Arthur J. Hoane , Paul D'Arcy , Sabin D. Iancu , Shenghong Wang
CPC classification number: G06F9/3851 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3885 , G06F9/46
Abstract: A processing device identifies a set of software threads having instructions waiting to issue. For each software thread in the set of the software threads, the processing device binds the software thread to an available hardware context in a set of hardware contexts and stores an identifier of the available hardware context bound to the software thread to a next available entry in an ordered list. The processing device reads an identifier stored in an entry of the ordered list. Responsive to an instruction associated with the identifier having no dependencies with any other instructions among the instructions waiting to issue, the processing device issues the instruction waiting to issue to the hardware context associated with the identifier.
Abstract translation: 处理设备识别具有等待发布的指令的一组软件线程。 对于软件线程集合中的每个软件线程，处理设备将软件线程绑定到一组硬件上下文中的可用硬件上下文，并将绑定到软件线程的可用硬件上下文的标识符存储到下一个可用条目中 有序列表。 处理装置读取存储在有序列表的条目中的标识符。 响应于等待发布的指令中与标识符相关联的与任何其他指令无关的指令，处理设备发出等待发布到与标识符相关联的硬件上下文的指令。
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