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公开(公告)号：US20060179396A1
公开(公告)日：2006-08-10
申请号：US11350149
申请日：2006-02-08
IPC分类号： H03M13/00
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/or preceding sub tree.
摘要翻译： 一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是 逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /或前一个子树。
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公开(公告)号：US20100237700A1
公开(公告)日：2010-09-23
申请号：US12754054
申请日：2010-04-05
CPC分类号： G01R31/2889 , G01R31/318513 , H01L2924/0002 , Y10T307/492 , H01L2924/00
摘要： A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.
摘要翻译： 一个信号重启芯片包括一个输入端; 至少一个反相器串联连接到输入端; 以及连接到测试使能信号的至少一个开关，所述至少一个开关被配置为在测试使能信号为导通的情况下允许连接到所述输入的信号传播通过所述至少一个逆变器。 3维集成电路包括第一芯片，第一芯片包括默认电压电平和多个布线层; 和第二芯片，所述第二芯片包括至少一个中继器，所述中继器连接到所述默认电压电平。
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公开(公告)号：US20080256413A1
公开(公告)日：2008-10-16
申请号：US11868637
申请日：2007-10-08
IPC分类号： H03M13/00
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), Which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal, of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.
摘要翻译： 一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是 逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到相邻的邻近树（12）路径的次级输入（32）的信号组合 和/我们的前一个子树。
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14.发明授权Method for evaluating storage cell design using a wordline timing and cell access detection circuit 失效使用字线定时和单元访问检测电路评估存储单元设计的方法公开(公告)号：US07414904B2
公开(公告)日：2008-08-19
申请号：US11609598
申请日：2006-12-12
申请人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
发明人： Sebastian Ehrenreich , Jente B Kuang , Chun-Tao Li , Hung Cai Ngo
IPC分类号： G11C7/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/02 , G11C29/025 , G11C29/50012
摘要： A method for storage cell design evaluation provides accurate information about state changes in static storage cells. A wordline select pulse is propagated along the wordline select path of the test row to an output driver circuit, in order to test the clock and/or address timing of the row, so that variation of access timing, read stability and writeability with wordline strength/access voltage can be determined. An access detection cell holds the input of the output driver circuit until a simulated access operation activated by the wordline select pulse is complete. Multiple test rows may be cascaded among columns to provide a long delay line or ring oscillator for improved measurement resolution.
摘要翻译： 用于存储单元设计评估的方法提供关于静态存储单元中的状态变化的准确信息。 字线选择脉冲沿着测试行的字线选择路径传播到输出驱动器电路，以便测试该行的时钟和/或地址时序，使得访问时序，读取稳定性和可写性与字线强度的变化 /访问电压可以确定。 访问检测单元保持输出驱动器电路的输入，直到由字线选择脉冲激活的模拟访问操作完成。 多个测试行可以在列之间级联，以提供长延迟线或环形振荡器，以提高测量分辨率。
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公开(公告)号：US20080048729A1
公开(公告)日：2008-02-28
申请号：US11782910
申请日：2007-07-25
申请人： Sebastian Ehrenreich
发明人： Sebastian Ehrenreich
IPC分类号： H03K5/22
CPC分类号： G03F7/70516
摘要： A comparator circuit for comparing a first voltage signal to a second voltage signal is described. The comparator circuit includes a first comparator and a second comparator and a selection unit for selecting one of the comparators depending on a selection condition. The invention also provides a method for operating a comparator circuit.
摘要翻译： 描述用于将第一电压信号与第二电压信号进行比较的比较器电路。 比较器电路包括第一比较器和第二比较器以及用于根据选择条件选择比较器之一的选择单元。 本发明还提供了一种用于操作比较器电路的方法。
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公开(公告)号：US08513663B2
公开(公告)日：2013-08-20
申请号：US12754054
申请日：2010-04-05
CPC分类号： G01R31/2889 , G01R31/318513 , H01L2924/0002 , Y10T307/492 , H01L2924/00
摘要： A signal repowering chip comprises an input; at least one inverter connected in series to the input; and at least one switch connected to a test enable signal, the at least one switch configured to allow a signal connected to the input to propagate through the at least one inverter in the event that the test enable signal is on. A 3-dimensional integrated circuit comprises a first chip, the first chip comprising a default voltage level and a plurality of wiring layers; and a second chip, the second chip comprising at least one repeater, the repeater being connected to the default voltage level.
摘要翻译： 一个信号重启芯片包括一个输入端; 至少一个反相器串联连接到输入端; 以及连接到测试使能信号的至少一个开关，所述至少一个开关被配置为在测试使能信号为导通的情况下允许连接到所述输入的信号传播通过所述至少一个逆变器。 3维集成电路包括第一芯片，第一芯片包括默认电压电平和多个布线层; 和第二芯片，所述第二芯片包括至少一个中继器，所述中继器连接到所述默认电压电平。
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17.发明授权Wordline booster design structure and method of operating a wordine booster circuit 有权Wordline助推器设计结构和操作字提升电路的方法公开(公告)号：US07921388B2
公开(公告)日：2011-04-05
申请号：US11847759
申请日：2007-08-30
CPC分类号： G11C5/145 , G11C8/08 , G11C11/413
摘要： The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.
摘要翻译： 本发明涉及一种字线升压电路，特别是一种SRAM字线升压电路，它包括用于移动电荷存储元件（50）的电压电平的驱动元件（20），用于存储产生升压电压（Vb）所需的电荷， ，用于控制充电元件（40）的开关状态的反馈元件（30），其中所述充电元件（40）可在第一时间间隔期间的关断状态和第二时间间隔期间的接通状态之间主动切换 以及用于将升压电压提供给存储装置（200）的至少一个字线驱动电路（100）的输出端口（14）。 本发明还涉及这种字线升压电路的操作方法以及具有字线升压电路的集成电路，特别是SRAM存储器阵列上的存储器阵列实现。
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公开(公告)号：US07755408B2
公开(公告)日：2010-07-13
申请号：US11868637
申请日：2007-10-08
CPC分类号： G06F1/10 , H03K5/15013 , H03K19/007
摘要： A signal distribution tree structure for distributing signals within a plurality of signal tree branches to a plurality of signal sinks, wherein the signal in subsequent sub trees (11) is driven by a preceding amplifier (2), which is characterized in that the amplifiers are logic gates (3), which combines the signals of a preferred input (31) connected to a preceding logic gate in the signal path with a signal of a secondary input (32) connected to an adjacent tree (12) path of a neighboring and/our preceding sub tree.
摘要翻译： 一种信号分配树结构，用于将多个信号树分支中的信号分配到多个信号宿，其中后续子树（11）中的信号由前一放大器（2）驱动，其特征在于放大器是 逻辑门（3），其将连接到信号路径中的先前逻辑门的优选输入（31）的信号与连接到邻近的相邻树（12）路径的次级输入（32）的信号组合，以及 /我们以前的子树。
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公开(公告)号：US07558138B1
公开(公告)日：2009-07-07
申请号：US12242564
申请日：2008-09-30
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/12 , G11C29/1201 , G11C29/32 , G11C2029/1204 , G11C2029/3202
摘要： A method for bypassing a memory array in a circuit having a global bit line, a test port configured to output a logic test, a memory portion connected to the global bit line via a word line, a header device being connected to the global bit line via a pre-charge signal, the header device being configured to recharge the global bit line. A gating signal is sent to a gating device connected to the header device. The gating device is switched to a test mode upon receipt of the gating signal. The bypass data signal is sent to an evaluating device connected to the gating device, the evaluating device being configured to output a logic test. The logic test is output through the test port upon receipt of bypass data signal.
摘要翻译： 一种用于绕过具有全局位线的电路中的存储器阵列的方法，被配置为输出逻辑测试的测试端口，经由字线连接到全局位线的存储器部分，连接到全局位线的标题设备 通过预充电信号，头部设备被配置为对全局位线进行再充电。 选通信号被发送到连接到报头装置的选通装置。 门控装置在接收到门控信号时切换到测试模式。 旁路数据信号被发送到连接到选通装置的评估装置，评估装置被配置为输出逻辑测试。 接收到旁路数据信号后，逻辑测试通过测试端口输出。
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20.发明申请DESIGN STRUCTURE FOR IMPROVING PERFORMANCE OF SRAM CELLS, SRAM CELL, SRAM ARRAY, AND WRITE CIRCUIT 失效提高SRAM单元，SRAM单元，SRAM阵列和写入电路性能的设计结构公开(公告)号：US20090154263A1
公开(公告)日：2009-06-18
申请号：US11954672
申请日：2007-12-12
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to switch the write circuit on and off. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage.
摘要翻译： 描述体现在机器可读介质中以改善包括多个SRAM单元的SRAM单元或SRAM阵列的性能的设计结构。 该设计结构包括用于SRAM单元或SRAM阵列的写入电路。 写入电路包括用于开启和关闭写入电路的门。 电池由第一高电压供电。 该单元可通过连接到写入电路的至少一个位线进行读取和写入操作。 该单元进一步可由至少一个字线寻址，以便通过位线访问该单元。 为了访问单元进行读或写操作，字线由第一较高电压提供，位线由第二较低电压提供。 在写操作期间，写电路由第一较高电压驱动，同时位线仍处于较低电压。
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