公开(公告)号：US5378651A

公开(公告)日：1995-01-03

申请号：US56697

申请日：1993-04-30

申请人： Paul D. Agnello ,  Detlev A. Gruetzmacher ,  Tung-Sheng Kuan ,  Thomas O. Sedgwick

发明人： Paul D. Agnello ,  Detlev A. Gruetzmacher ,  Tung-Sheng Kuan ,  Thomas O. Sedgwick

IPC分类号： C30B25/02 ,  H01L21/205 ,  H01L21/203

CPC分类号： C30B29/06 ,  C30B25/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02636

摘要： A system and method for growing low defect density epitaxial layers of Si on imperfectly cleaned Si surfaces by either selective or blanket deposition at low temperatures using the APCVD process wherein a first thin, e.g., 10 nm, layer of Si is grown on the surface from silane or disilane, followed by the growing of the remainder of the film from dichlorosilane (DCS) at the same low temperature, e.g., 550.degree. C. to 850.degree. C. The subsequent growth of the second layer with DCS over the first layer, especially if carried out immediately in the very same deposition system, will not introduce additional defects and may be coupled with high and controlled n-type doping which is not available in a silane-based system. Further, in order to achieve an optimal trade-off between the need for an inert ambience to promote silane reaction at low temperature and the need for a hydrogen ambience to prevent surface oxidation from inadvertant residual impurities, depositions are carried out in an ambience composed primarily of He but always containing some H.sub.2. Also, the relative deposition rates on a patterned surface of polycrystalline Si on insulator areas and single crystal Si on single crystal seed areas, when using the reactant silane, are dependent on the temperature of deposition and the relative concentrations of hydrogen and inert gas, e.g., helium, in the ambient gas, and can be controlled by regulating these parameters.

摘要翻译： 通过使用APCVD工艺在低温下通过选择性或覆盖沉积在不完全清洁的Si表面上生长Si的低缺陷密度外延层的系统和方法，其中在表面上生长第一薄例如10nm的Si层， 硅烷或乙硅烷，然后在相同的低温（例如550℃至850℃）下从二氯硅烷（DCS）中生长剩余的膜。随后在第一层上用DCS生长第二层， 特别是如果在相同的沉积系统中立即进行，则不会引入额外的缺陷，并且可能与在硅烷系统中不可用的高且受控的n型掺杂相结合。 此外，为了在惰性气氛促进低温下的硅烷反应的需要和氢气氛的需要之间实现最佳的权衡，以防止表面氧化从不经意的残留杂质，沉积在主要组成的环境中进行 他总是含有一些H2。 此外，当使用反应物硅烷时，在单晶种子区域上的多晶Si绝缘体区域和单晶Si的图案化表面上的相对沉积速率取决于沉积温度和氢气和惰性气体的相对浓度，例如 ，氦气，在环境气体中，并且可以通过调节这些参数来控制。

公开(公告)号：US07265417B2

公开(公告)日：2007-09-04

申请号：US10867772

申请日：2004-06-16

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L27/01

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

公开(公告)号：US06686617B2

公开(公告)日：2004-02-03

申请号：US09878804

申请日：2001-06-11

申请人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

发明人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

IPC分类号： H01L27108

CPC分类号： H01L27/10861 ,  H01L21/823443 ,  H01L21/82345 ,  H01L27/10873 ,  H01L27/10894

摘要： A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

摘要翻译： 在同一半导体芯片上制造紧凑型存储器和高性能逻辑的工艺。 该过程包括在存储器区域中形成存储器件，在存储区域和逻辑区域两者之间形成间隔氮化物层和保护层，去除逻辑区域上的保护层以暴露衬底，以及形成逻辑器件 逻辑区域。 将钴或钛金属施加在逻辑区域的所有水平表面上并退火，形成硅化物，其中金属沉积在硅或多晶硅区域上，并且任何未反应的金属被去除。 然后将最上面的氮化物层施加在存储器和逻辑区域两者上，然后在逻辑区域中用填料覆盖。 还公开了由该方法的各种实施方案产生的芯片结构。

公开(公告)号：US06406962B1

公开(公告)日：2002-06-18

申请号：US09761931

申请日：2001-01-17

申请人： Paul D. Agnello ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Paul D. Agnello ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21336

CPC分类号： H01L29/78648 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/78642

摘要： The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.

摘要翻译： 本发明涉及一种形成具有垂直沟槽形成的双栅极的一个或多个FET的装置和方法，其中多个氮化物层具有周期性地设置在其上的氧化物标记蚀刻停止层，从而使FET具有 多个可选择的栅极长度。 本发明提供控制和形成尺寸缩小到约5nm至约100nm，优选约5nm至约50nm的栅极长度。 具有氧化物蚀刻停止层的多个衬垫氮化物层通过蚀刻衬垫氮化物层中的多个通孔来提供本FET连接到具有对应于所使用的栅极长度的各种连接深度的多个触点 由此这些通孔在选定的蚀刻停止层处停止以提供适于与所选择的这些触点连接的通孔。 附加的栅极材料可以沉积在所选择的多个氮化物层的顶表面上，以允许与任何给定FET的栅电极的接触。

公开(公告)号：US06261951B1

公开(公告)日：2001-07-17

申请号：US09472346

申请日：1999-12-27

申请人： Leena P. Buchwalter ,  Barbara Luther ,  Paul D. Agnello ,  John P. Hummel ,  Terence Lawrence Kane ,  Dirk Karl Manger ,  Paul Stephen McLaughlin ,  Anthony Kendall Stamper ,  Yun Yu Wang

发明人： Leena P. Buchwalter ,  Barbara Luther ,  Paul D. Agnello ,  John P. Hummel ,  Terence Lawrence Kane ,  Dirk Karl Manger ,  Paul Stephen McLaughlin ,  Anthony Kendall Stamper ,  Yun Yu Wang

IPC分类号： H01L214763

CPC分类号： H01L21/3185 ,  H01L21/0445 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76834

摘要： The present invention utilizes a reducing plasma treatment step to enhance the adhesion of a subsequently deposited inorganic barrier film to a copper wire or via present in a semiconductor interconnect structure such as a dual damascene structure. Interconnect structure comprising a material layer of Cu, Si and O, as essential elements, is formed between said copper wire or via and the inorganic barrier film.

公开(公告)号：US5576579A

公开(公告)日：1996-11-19

申请号：US371627

申请日：1995-01-12

申请人： Paul D. Agnello ,  Cyril Cabral, Jr. ,  Alfred Grill ,  Christopher V. Jahnes ,  Thomas J. Licata ,  Ronnen A. Roy

发明人： Paul D. Agnello ,  Cyril Cabral, Jr. ,  Alfred Grill ,  Christopher V. Jahnes ,  Thomas J. Licata ,  Ronnen A. Roy

IPC分类号： H01L21/28 ,  H01L21/46 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/94 ,  H01L29/43

CPC分类号： H01L21/28185 ,  H01L21/28061 ,  H01L21/28202 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4941 ,  H01L29/4958 ,  H01L29/513 ,  H01L29/518 ,  H01L29/94

摘要： A multilayer structure having an oxygen or dopant diffusion barrier fabricated of an electrically conductive, thermally stable material of refractory metal-silicon-nitrogen which is resistant to oxidation, prevents out-diffusion of dopants from silicon and has a wide process window wherein the refractory metal is selected from Ta, W, Nb, V, Ti, Zr, Hf, Cr and Mo.

摘要翻译： 具有氧化或掺杂剂扩散阻挡层的多层结构，其由耐氧化的难熔金属 - 硅 - 氮的导电的，热稳定的材料制成，防止掺杂剂从硅的扩散扩散，并且具有宽的工艺窗口，其中难熔金属 选自Ta，W，Nb，V，Ti，Zr，Hf，Cr和Mo。

公开(公告)号：US08227792B2

公开(公告)日：2012-07-24

申请号：US12031530

申请日：2008-02-14

申请人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： H01L31/00

CPC分类号： H01L21/324 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66893 ,  H01L29/78603

摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

摘要翻译： 提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。 所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。 将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。 在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

公开(公告)号：US07361556B2

公开(公告)日：2008-04-22

申请号：US11495518

申请日：2006-07-31

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66484 ,  H01L29/66795 ,  H01L29/78654 ,  H01L29/78687

摘要： A double gated silicon-on-insulator (SOI) MOSFET is fabricated by forming epitaxially grown channels, followed by a damascene gate. The double gated MOSFET features narrow channels, which increases current drive per layout width and provides low out conductance.

摘要翻译： 通过形成外延生长的通道，随后是镶嵌栅极，制造双栅极绝缘体上硅（SOI）MOSFET。 双门控MOSFET具有窄通道，这增加了每个布局宽度的电流驱动，并提供了低导通电压。

公开(公告)号：US07112845B2

公开(公告)日：2006-09-26

申请号：US10064171

申请日：2002-06-18

申请人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

发明人： James W. Adkisson ,  Paul D. Agnello ,  Arne W. Ballantine ,  Rama Divakaruni ,  Erin C. Jones ,  Jed H. Rankin

IPC分类号： H01L27/01

CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66818

摘要： A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is achieved by silicide sidewalls or liners while low gate to junction capacitance is achieved by recessing the silicide and polysilicon dual gate structure from the source and drain region edges.

公开(公告)号：US06946373B2

公开(公告)日：2005-09-20

申请号：US10300189

申请日：2002-11-20

申请人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

发明人： Paul D. Agnello ,  Stephen W. Bedell ,  Robert H. Dennard ,  Anthony G. Domenicucci ,  Keith E. Fogel ,  Devendra K. Sadana

IPC分类号： C30B25/02 ,  C30B29/52 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/337 ,  H01L21/84 ,  H01L21/477

CPC分类号： H01L21/324 ,  C30B25/02 ,  C30B29/52 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L29/66893 ,  H01L29/78603

摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

摘要翻译： 提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。 所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。 将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。 在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。