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    IN-DATAGRAM CRITICAL-SIGNALING USING PULSE-COUNT-MODULATION FOR I3C BUS
    11.
    发明申请
    IN-DATAGRAM CRITICAL-SIGNALING USING PULSE-COUNT-MODULATION FOR I3C BUS 审中-公开

    公开(公告)号：US20190238362A1

    公开(公告)日：2019-08-01

    申请号：US15882494

    申请日：2018-01-29

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Richard Dominic Wietfeldt ,  Radu Pitigoi-Aron

    IPC: H04L12/40 ,  H04L25/49 ,  G06F13/42 ,  H04L1/16

    Abstract: Systems, methods, and apparatus are described that enable a device to indicate availability of priority data to be communicated over a half-duplex serial bus without waiting for an ongoing transmission to be completed. In-datagram critical signaling is accommodated without breaking backward compatibility. A method implemented at a transmitting device coupled to a serial bus includes transmitting a data byte over a first line of the serial bus to a receiving device in accordance with a clock signal transmitted by a master device on a second line of the serial device, detecting a first pulse on the first line of the serial bus during a cycle of the clock signal designated for an acknowledgement or negative acknowledgement by the second device, and processing an alert indicated by the first pulse.

    Dynamically adjustable multi-line bus shared by multi-protocol devices
    13.
    发明授权
    Dynamically adjustable multi-line bus shared by multi-protocol devices 有权

    公开(公告)号：US10007628B2

    公开(公告)日：2018-06-26

    申请号：US14728777

    申请日：2015-06-02

    Applicant: QUALCOMM Incorporated

    Inventor： Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

    IPC: G06F13/00 ,  G06F13/364 ,  G06F13/42

    CPC classification number: G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  G06F13/4295

    Abstract: A device is provided that has a bus including a first line and a second line. A first set of devices are coupled to the bus and, in a first mode of operation, configured to use the first line for data transmissions and use the second line for a first clock signal. One or more additional lines are connected between two or more of the devices in the first set of devices for transmitting signaling between the two or more devices. A second set of devices are configured to use the bus and at least one of the additional lines for data transmissions in a second mode of operation, where in the second mode of operation symbols are encoded across the first line, the second line, and the at least one of the additional lines.

    HARD RESET OVER I3C BUS
    14.
    发明申请
    HARD RESET OVER I3C BUS 审中-公开

    公开(公告)号：US20180173667A1

    公开(公告)日：2018-06-21

    申请号：US15658883

    申请日：2017-07-25

    Applicant: QUALCOMM Incorporated

    Inventor： Lalan Jee Mishra ,  Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt

    IPC: G06F13/42 ,  G06F1/32

    CPC classification number: G06F13/4282 ,  G06F1/3293 ,  G06F2213/0016

    Abstract: Systems, methods, and apparatus are described that enable communication of in-band reset signals over a serial bus. A method performed at a slave device coupled to the serial bus includes configuring a reset controller to operate in one of plural modes, identifying a first reset pattern in signaling received from a multi-wire serial bus, complying with one or more transmissions defined by the protocol, asserting a reset input of a processing circuit in the slave device responsive to an identification of the first reset pattern when the reset controller is operated in a first mode, and ignoring the first reset pattern when the reset controller is operated in a second mode. The signaling received from the multi-wire serial bus may include one or more transmissions defined by a protocol used on the multi-wire serial bus. The reset controller may operate autonomously from the processing circuit in the first mode.

    Sensors global bus
    15.
    发明授权
    Sensors global bus 有权

    公开(公告)号：US09734121B2

    公开(公告)日：2017-08-15

    申请号：US14694618

    申请日：2015-04-23

    Applicant: QUALCOMM Incorporated

    Inventor： Radu Pitigoi-Aron ,  Richard Dominic Wietfeldt ,  Douglas Wayne Hoffman

    IPC: G06F13/42

    CPC classification number: G06F13/4295 ,  G06F13/4291 ,  G06F2213/0016 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A first command is transmitted to devices coupled to a serial bus operated in a first mode in accordance with a first protocol to cause the serial bus to be operated in a second mode. After communicating in accordance with a second protocol while the serial bus is operated in the second mode, a second command is transmitted to the plurality of devices in accordance with the first protocol to terminate the second mode. In the second mode, extra symbols inserted into a sequence of symbols transmitted on the serial bus prevent the occurrence of an unintended signaling state on the serial bus. Pulses transmitted on a wire of the serial bus in the second mode may have their duration limited such that a filter of a second device suppresses the limited-duration pulses.

    TEST FOR 50 NANOSECOND SPIKE FILTER
    17.
    发明申请
    TEST FOR 50 NANOSECOND SPIKE FILTER 审中-公开
    测试50 NANOSECOND SPIKE过滤器

    公开(公告)号：US20160364305A1

    公开(公告)日：2016-12-15

    申请号：US15179470

    申请日：2016-06-10

    Applicant: QUALCOMM Incorporated

    Inventor： Radu Pitigoi-Aron

    IPC: G06F11/22 ,  G06F1/08 ,  G06F13/40 ,  G06F13/364 ,  G06F13/42

    CPC classification number: G06F11/221 ,  G06F1/08 ,  G06F11/2289 ,  G06F11/263 ,  G06F13/364 ,  G06F13/404 ,  G06F13/4282 ,  G06F13/4291

    Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. A method of testing a spike filter in a legacy I2C device includes generating a command to be transmitted on a serial bus in accordance with an I2C protocol, where the command includes an address corresponding to the legacy slave device, merging the command with a sequence of pulses to obtain a test signal, transmitting the test signal on the serial bus, and determining the efficacy of a spike filter in the first slave device based on whether the legacy slave device acknowledges the test signal. Each pulse in the sequence of pulses has a duration that is less than 50 ns. The spike filter is expected to suppress pulses that have a duration of less than 50 ns.

    Abstract translation: 描述了提供内部集成电路（I2C）总线的改进性能的系统，方法和装置。 在传统I2C设备中测试尖峰滤波器的方法包括根据I2C协议生成要在串行总线上发送的命令，其中该命令包括与传统从设备相对应的地址，将该命令与一系列 脉冲以获得测试信号，在串行总线上发送测试信号，以及基于传统从设备是否确认测试信号来确定尖峰滤波器在第一从设备中的功效。 脉冲序列中的每个脉冲具有小于50ns的持续时间。 预期尖峰滤波器抑制持续时间小于50ns的脉冲。

    System and methods of reducing energy consumption by synchronizing sensors
    18.
    发明授权
    System and methods of reducing energy consumption by synchronizing sensors 有权
    通过同步传感器降低能耗的系统和方法

    公开(公告)号：US09436214B2

    公开(公告)日：2016-09-06

    申请号：US14304699

    申请日：2014-06-13

    Applicant: QUALCOMM, Incorporated

    Inventor： Radu Pitigoi-Aron ,  Leonid Sheynblat ,  Carlos Manuel Puig ,  Justin Black ,  Rashmi Kulkarni

    IPC: G06F1/12 ,  G06F1/14 ,  G06F1/32

    CPC classification number: G06F1/12 ,  G01D21/00 ,  G06F1/14 ,  G06F1/329 ,  Y02D10/24

    Abstract: Aspects of the invention are related to a method for synchronizing a first sensor clock of a first sensor. The exemplary method comprises: correcting the first sensor clock for a first time, transferring data from the first sensor, and correcting the first sensor clock for a second time, wherein a time interval between two corrections of the first sensor clock is selected such that the first sensor clock is sufficiently aligned with a processor clock of a processor over the time interval.

    Abstract translation: 本发明的方面涉及一种用于同步第一传感器的第一传感器时钟的方法。 该示例性方法包括：第一次校正第一传感器时钟，从第一传感器传送数据，并且第二次校正第一传感器时钟，其中选择第一传感器时钟的两次校正之间的时间间隔，使得 第一传感器时钟在时间间隔内与处理器的处理器时钟充分对齐。

    Batch operation across an interface
    19.
    发明授权
    Batch operation across an interface 有权

    公开(公告)号：US11513991B2

    公开(公告)日：2022-11-29

    申请号：US17061357

    申请日：2020-10-01

    Applicant: QUALCOMM Incorporated

    Inventor： Richard Dominic Wietfeldt ,  Lalan Jee Mishra ,  Radu Pitigoi-Aron

    IPC: G06F13/42

    Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals and control messages over a serial communication link. An apparatus includes a serial bus, and a controller configured to represent a series of signaling state of physical general-purpose input/output (GPIO) in a batch that comprises a sequence of virtual GPIO messages and control messages, generate a first header that includes timing information configured to control timing of execution of the batch, transmit the first header over a communication link, and transmit the batch over the communication link.

    Techniques for synchronizing slave devices
    20.
    发明授权
    Techniques for synchronizing slave devices 有权

    公开(公告)号：US10707984B2

    公开(公告)日：2020-07-07

    申请号：US16025863

    申请日：2018-07-02

    Applicant: QUALCOMM Incorporated

    Inventor： Radu Pitigoi-Aron

    IPC: H04J3/06 ,  H04Q9/04 ,  G01D21/00 ,  G06F1/14 ,  G06F1/12 ,  H04L29/08 ,  H04W56/00 ,  H04W84/18

    Abstract: Disclosed are methods and apparatus for calculating sensor timing corrections at a sensor device. The methods and apparatus determine a sampling period as a number of cycles of an internal clock counted while a configured number of samples is captured in a slave device, determine a time interval between samples using an offset from a time of an observed occurrence of a hardware event on a communication link, the offset being received in a command from a master device, and adjust the time interval between samples by iterative digital approximation to correct for differences between timing of the slave device and the master device while concurrently calculating a watermark time corresponding to a sample start time configured by the master device for one or more slave devices.

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