公开(公告)号：US20170041897A1

公开(公告)日：2017-02-09

申请号：US15299382

申请日：2016-10-20

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Leonid Sheynblat ,  Carlos Puig ,  Justin Black ,  Rashmi Kulkarni

IPC: H04W56/00

CPC classification number: H04W56/0045 ,  G06F1/12 ,  G06F1/14 ,  H04J3/0685 ,  H04Q9/00 ,  H04Q2209/75 ,  H04W56/0015 ,  H04W84/18

Abstract: Disclosed are methods and apparatus for transmitting sensor timing correction messages with a host controller. The methods and apparatus determine synchronization messages that are transmitted to a sensor coupled with the host controller via an interface, where the messages indicate a beginning of a synchronization period for synchronizing timing of the host controller and the sensor. Additionally, a delay time message is determined that indicates a time delay between the beginning of the synchronization period and an actual transmission time of the synchronization message. The synchronization message is transmitted with the delay time message in an information message to the sensor, where information message is configured to allow the sensor to correct timing of a sensor timer by accounting for the delay time.

Abstract translation: 公开了用于利用主机控制器发送传感器定时校正消息的方法和装置。 方法和装置确定经由接口传送到与主控制器耦合的传感器的同步消息，其中消息指示用于同步主机控制器和传感器的定时的同步周期的开始。 此外，确定延迟时间消息，其指示同步时段的开始和同步消息的实际发送时间之间的时间延迟。 同步消息与信息消息中的延迟时间消息一起发送到传感器，其中信息消息被配置为允许传感器通过计算延迟时间来校正传感器定时器的定时。

公开(公告)号：US20170041688A1

公开(公告)日：2017-02-09

申请号：US15299408

申请日：2016-10-20

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Leonid Sheynblat ,  Carlos Puig ,  Justin Black ,  Rashmi Kulkarni

IPC: H04Q9/00 ,  H04J3/06

CPC classification number: H04Q9/00 ,  G06F1/14 ,  G06F1/3234 ,  H04J3/0661 ,  H04J3/0685 ,  H04Q9/04 ,  H04Q2209/30 ,  H04Q2209/753 ,  H04Q2209/826 ,  H04Q2209/883 ,  H04W84/18

Abstract: Disclosed are methods and apparatus for synchronizing a controller and sensors in a system. A timestamp is provided in a host controller of an interface event on an interface coupled with host controller through detecting a message from a sensor on the interface that identifies the issuance of the interface event caused by the sensor at a first time. In response, the controller issues first and second events on the interface at respective second and third times, while concurrently counting cycles of a clock in the controller after each issuance. The controller also receives a first and second sensor counts representing the internal sensor clock times noted for the first and second events. The controller may then accurately calculate the timestamp of the interface event corresponding to the first time based on both internal controller counts and the sensor counts without needing a timestamp from the sensor directly.

Abstract translation: 公开了用于使系统中的控制器和传感器同步的方法和装置。 在与主机控制器耦合的接口的接口事件的主机控制器中，通过从接口上的传感器检测到消息，在第一时间识别由传感器引起的接口事件的发出，提供时间戳。 作为响应，控制器在相应的第二和第三次在接口上发出第一和第二事件，同时在每次发布之后同时对控制器中的时钟的周期进行计数。 控制器还接收表示第一和第二事件所指示的内部传感器时钟时间的第一和第二传感器计数。 然后，控制器可以基于内部控制器计数和传感器计数来准确地计算与第一次相对应的接口事件的时​​间戳，而不需要直接来自传感器的时间戳。

公开(公告)号：US20160124896A1

公开(公告)日：2016-05-05

申请号：US14925612

申请日：2015-10-28

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Justin Black

IPC: G06F13/42 ,  G06F13/364

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  H04L25/4923

Abstract: A device is provided comprising a shared bus including a first and a second line, a first subset of devices and a second subset of devices coupled to the shared bus. The first subset of devices may be configured to operate according to a first protocol mode. The second subset of devices may be configured to operate according to a second protocol mode, wherein the second protocol mode is distinct from the first protocol mode. A first device within the first subset of devices may include a receiver circuit adapted to adjust a signal transition occurring on the first line while the second line is in a first logical state so that the signal transition instead occurs when the second line is in a second logical state. The signal transition is adjusted only if it occurs within a threshold amount of time from a second transition on the second line.

Abstract translation: 提供了一种包括共享总线的设备，该共享总线包括第一和第二线路，设备的第一子集以及耦合到共享总线的设备的第二子集。 设备的第一子集可以被配置为根据第一协议模式进行操作。 设备的第二子集可以被配置为根据第二协议模式进行操作，其中第二协议模式与第一协议模式不同。 设备的第一子集内的第一设备可以包括接收机电路，其适于在第二行处于第一逻辑状态时调整发生在第一行上的信号转换，从而当第二行处于第二行时发生信号转换 逻辑状态。 只有当信号转换发生在从第二条线路上的第二转变开始的阈值时间内时才调整信号转换。

公开(公告)号：US10250375B2

公开(公告)日：2019-04-02

申请号：US15273015

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Justin Black ,  Cheng-Han Wang ,  Jeongsik Yang

IPC: H04L7/00 ,  H03K19/21 ,  H03L7/00 ,  H03L7/081 ,  H03L7/14 ,  H03L7/22 ,  H04W52/02

Abstract: An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.

公开(公告)号：US20160370845A1

公开(公告)日：2016-12-22

申请号：US15251757

申请日：2016-08-30

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Leonid Sheynblat ,  Carlos Puig ,  Justin Black ,  Rashmi Kulkarni

IPC: G06F1/32 ,  G06F1/08 ,  G06F1/12

CPC classification number: G06F1/12 ,  G01D21/00 ,  G06F1/14 ,  G06F1/329 ,  Y02D10/24

Abstract: Disclosed aspects relate to methods and apparatus for correcting a first sensor clock of a first sensor. The disclosed methods and apparatus effectuate receiving first and seconds signals in a sensor from a processor at known different times related to the timing of the processor clock. Based on the measured time interval between the times of the first and second signals as determined by the sensor, a clock correction factor may be determined in the sensor for correcting the timing of the sensor clock to be synchronized with the processor clock.

Abstract translation: 公开的方面涉及用于校正第一传感器的第一传感器时钟的方法和装置。 所公开的方法和装置实现在与处理器时钟的定时有关的已知不同时间处理器中从处理器接收传感器中的第一和第二信号。 基于由传感器确定的第一和第二信号的时间之间的测量时间间隔，可以在传感器中确定时钟校正因子，用于校正要与处理器时钟同步的传感器时钟的定时。

公开(公告)号：US09990330B2

公开(公告)日：2018-06-05

申请号：US14925612

申请日：2015-10-28

Applicant: QUALCOMM Incorporated

Inventor： Radu Pitigoi-Aron ,  Justin Black

IPC: G06F13/00 ,  G06F13/42 ,  G06F13/364 ,  H04L25/49

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4282 ,  H04L25/4923

Abstract: A device is provided comprising a shared bus including a first and a second line, a first subset of devices and a second subset of devices coupled to the shared bus. The first subset of devices may be configured to operate according to a first protocol mode. The second subset of devices may be configured to operate according to a second protocol mode, wherein the second protocol mode is distinct from the first protocol mode. A first device within the first subset of devices may include a receiver circuit adapted to adjust a signal transition occurring on the first line while the second line is in a first logical state so that the signal transition instead occurs when the second line is in a second logical state. The signal transition is adjusted only if it occurs within a threshold amount of time from a second transition on the second line.

公开(公告)号：US10416750B2

公开(公告)日：2019-09-17

申请号：US14498510

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Justin Black ,  Rashmi Kulkarni ,  Leonid Sheynblat

IPC: G06F1/3234 ,  G01D9/00 ,  G06F1/3293

Abstract: Disclosed is a method and apparatus for power-efficiently processing sensor data. In one embodiment, the operations implemented include: configuring a sensor fusion engine and a peripheral controller with a general purpose processor; placing the general purpose processor into a low-power sleep mode; reading data from a sensor and storing the data into a companion memory with the peripheral controller; processing the data in the companion memory with the sensor fusion engine; and awaking the general purpose processor from the low-power sleep mode.

公开(公告)号：US20180083763A1

公开(公告)日：2018-03-22

申请号：US15273015

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Justin Black ,  Cheng-Han Wang ,  Jeongsik Yang

IPC: H04L7/00 ,  H03L7/00 ,  H03K19/21

CPC classification number: H04L7/0008 ,  H03K19/21 ,  H03L7/00 ,  H03L7/0812 ,  H03L7/143 ,  H03L7/22 ,  H04W52/02

Abstract: An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.

公开(公告)号：US09436214B2

公开(公告)日：2016-09-06

申请号：US14304699

申请日：2014-06-13

Applicant: QUALCOMM, Incorporated

Inventor： Radu Pitigoi-Aron ,  Leonid Sheynblat ,  Carlos Manuel Puig ,  Justin Black ,  Rashmi Kulkarni

IPC: G06F1/12 ,  G06F1/14 ,  G06F1/32

CPC classification number: G06F1/12 ,  G01D21/00 ,  G06F1/14 ,  G06F1/329 ,  Y02D10/24

Abstract: Aspects of the invention are related to a method for synchronizing a first sensor clock of a first sensor. The exemplary method comprises: correcting the first sensor clock for a first time, transferring data from the first sensor, and correcting the first sensor clock for a second time, wherein a time interval between two corrections of the first sensor clock is selected such that the first sensor clock is sufficiently aligned with a processor clock of a processor over the time interval.

Abstract translation: 本发明的方面涉及一种用于同步第一传感器的第一传感器时钟的方法。 该示例性方法包括：第一次校正第一传感器时钟，从第一传感器传送数据，并且第二次校正第一传感器时钟，其中选择第一传感器时钟的两次校正之间的时间间隔，使得 第一传感器时钟在时间间隔内与处理器的处理器时钟充分对齐。