Abstract:
Methods and apparatus for synchronizing dividers in different LO paths using pulse swallowing. One example apparatus generally includes a first path having a first frequency divider configured to generate a first divided signal from a first periodic signal; a second path having a second frequency divider configured to generate a second divided signal from a second periodic signal; a phase detector configured to compare phases of a first sensing signal based on the first divided signal and a second sensing signal based on the second divided signal and to generate a first trigger signal if the first and second sensing signals are out-of-phase; and a first pulse suppressor configured to suppress a pulse of the first periodic signal for at least one cycle in response to the first trigger signal to adjust a phase of the first divided signal.
Abstract:
Apparatuses and methods are disclosed regarding a multiband transmitter. In an example aspect, an apparatus for processing signals for wireless transmission includes a wireless interface device. The wireless interface device includes an upconverter, a tunable filter, and a driver amplifier. The upconverter has an output and is configured to upconvert a baseband frequency to a radio frequency based on a local oscillator signal. The tunable filter has an input and an output; the input of the tunable filter is coupled to the output of the upconverter. The driver amplifier has an input; the input of the driver amplifier is coupled to the output of the tunable filter.
Abstract:
An apparatus and a method are disclosed for synchronizing clock signals distributed within a wireless device. In some embodiments, a local oscillator (LO) clock signal is buffered and distributed to two or more transceivers within the wireless device. Each transceiver may include a configurable clock divider to divide the distributed LO clock signal and generate an output clock signal. A phase detector compares output clock signals from each of the configurable clock dividers and generates an output signal in accordance with a determined phase difference. The phase detector output signal may cause at least one of the configurable clock dividers to modify its respective output clock signal, and thereby synchronize output clock signals between different configurable clock dividers. In some embodiments, a clock signal from a configurable clock divider may be modified (shifted) by approximately 90 or 180 degrees.
Abstract:
A power amplifier bias circuit having high dynamic range and low memory is disclosed. In an exemplary embodiment, an apparatus includes an output stage configured to generate a biased RF signal based on a first DC signal and a filtered signal. The apparatus also includes a low pass filter configured to filter the biased RF signal to generate the filtered signal.
Abstract:
A method and apparatus are disclosed for a configurable amplifier. When operating in a first operating mode, the configurable amplifier may amplify a communication signal and may cancel or attenuate a second harmonic component associated with the communication signal. When operating in a second operating mode, the configurable amplifier may amplify the communication signal without cancelling or attenuating the second harmonic component associated with the communication signal.
Abstract:
Methods and circuits can down convert at least a first RF signal on a first path in a first frequency band to provide a first IF signal. A second RF signal on second path in a second frequency band can be down converted to provide a second IF signal. The first IF signal and the second IF signal are interspersed in the frequency domain, and the first frequency band is different from the second frequency band. A combiner can combine at least part of the first IF signal and the second IF signal to provide a combined signal on an output signal path for reception by a digital processing circuit. The first IF signal or second IF signal can be a Zero IF (ZIF), very low IF (VLIF), or Low IF (LIF) signal.
Abstract:
A global navigation satellite system (GNSS) receiver includes at least one GNSS antenna configured to receive input signaling from at least a first GNSS source and a second GNSS source; an in-phase/quadrature (I/Q) mixer coupled to the at least one GNSS antenna and configured to process the input signaling to obtain complex intermediate signaling; a first complex filter coupled to the I/Q mixer and configured to filter the complex intermediate signaling with respect to a first frequency range to obtain first real output signaling; a second complex filter coupled to the I/Q mixer and configured to filter the complex intermediate signaling with respect to a second frequency range to obtain second real output signaling; and a signal combiner coupled to the first and second complex filters and configured to generate combined real output signaling by combining the first real output signaling and the second real output signaling.
Abstract:
Apparatuses and methods are disclosed regarding a multiband transmitter. In an example aspect, an apparatus for processing signals for wireless transmission includes a wireless interface device. The wireless interface device includes an upconverter, a tunable filter, and a driver amplifier. The upconverter has an output and is configured to upconvert a baseband frequency to a radio frequency based on a local oscillator signal. The tunable filter has an input and an output; the input of the tunable filter is coupled to the output of the upconverter. The driver amplifier has an input; the input of the driver amplifier is coupled to the output of the tunable filter.
Abstract:
A radio frequency (RF) receiver, for example a satellite positioning system receiver, can be configured to use a single phase locked loop for generating an oscillator signal to perform downconversion of signals in two different frequency bands using two or more local oscillators. A first RF signal portion includes a first signal band and undergoes double downconversion using a first mixer and a second mixer, while a second RF signal portion includes a second signal band and undergoes single downconversion using a single mixer. A controller is configured to determine a first oscillator divider value and a second oscillator divider value to avoid a jammer frequency and frequency dividers are used to generate the two or more local oscillators.
Abstract:
A power amplifier bias circuit having high dynamic range and low memory is disclosed. In an exemplary embodiment, an apparatus includes an output stage configured to generate a biased RF signal based on a first DC signal and a filtered signal. The apparatus also includes a low pass filter configured to filter the biased RF signal to generate the filtered signal.