公开(公告)号：US11670351B1

公开(公告)日：2023-06-06

申请号：US17456773

申请日：2021-11-29

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu Pallerla ,  Anil Chowdary Kota ,  Changho Jung ,  Chulmin Jung

IPC: G11C7/10 ,  G11C5/14 ,  G11C7/12

CPC classification number: G11C7/106 ,  G11C5/14 ,  G11C7/1063 ,  G11C7/1087 ,  G11C7/12

Abstract: Various implementations provide systems and methods for reading data from memory bit cells. An example implementation includes a read circuit that provides a single-ended output from a sensing stage. The single-ended output is received by a reset-set (RS) latch, which also receives a virtual bit line signal. The single-ended output and the virtual bit line signal provide complementary inputs to the RS latch, and the RS latch stores a sensed bit, and the sensed bit may be driven onto a data bus.

公开(公告)号：US11610633B2

公开(公告)日：2023-03-21

申请号：US17367248

申请日：2021-07-02

Applicant: QUALCOMM Incorporated

Inventor： Xiao Chen ,  Chen-ju Hsieh ,  Sung Son ,  Chulmin Jung

IPC: G11C16/00 ,  G11C16/10 ,  G11C16/26 ,  G11C17/12 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24

Abstract: A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.

公开(公告)号：US11527282B2

公开(公告)日：2022-12-13

申请号：US17144077

申请日：2021-01-07

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Keejong Kim ,  Chulmin Jung ,  Ritu Chaba

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/10 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/418

Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

公开(公告)号：US11450359B1

公开(公告)日：2022-09-20

申请号：US17366864

申请日：2021-07-02

Applicant: QUALCOMM Incorporated

Inventor： Xiao Chen ,  Po-Hung Chen ,  Chen-ju Hsieh ,  David Li ,  Chulmin Jung ,  Ayan Paul

IPC: G11C7/10 ,  G11C7/12 ,  H03K19/173 ,  G11C5/14 ,  H03K19/0185

Abstract: Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal oxide semiconductor (PMOS) transistors. By using PMOS transistors instead of NMOS transistors at the applicable nodes, such implementations may avoid a voltage drop between VDD and the bitlines, thereby allowing the bitlines to reach a substantially full VDD voltage level when appropriate. Additionally, various implementations avoid dynamic nodes that share charge across NMOS transistors, thereby allowing a given bitline to reach a substantially full VDD voltage level when appropriate. Accordingly, some implementations may experience higher levels of writability and static noise margin than other implementations.

公开(公告)号：US20210343330A1

公开(公告)日：2021-11-04

申请号：US16862238

申请日：2020-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Bin Liang ,  Chi-Jui Chen

IPC: G11C11/4094 ,  G11C11/4074 ,  G11C11/4096 ,  G11C7/12 ,  G11C5/02

Abstract: Methods and apparatuses having an improved write assist scheme are presented. An apparatus includes a power supply node configured to provide power from a power supply to one memory cell to store data; a bitline configured to provide write data to the one memory cell in a write operation; and a discharge circuit configured to selectively discharge the power supply node to the bitline, based on the write data. A method to write into a memory cell with a write assist scheme includes providing power from a power supply to one memory cell via a power supply node, to store data; providing write data to the one memory cell via a bitline in a write operation; and discharging, selectively based on the write data, the power supply node to the bitline.

公开(公告)号：US11049552B1

公开(公告)日：2021-06-29

申请号：US16827959

申请日：2020-03-24

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta ,  Chulmin Jung

IPC: G11C7/12 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4097 ,  G11C7/10 ,  G11C11/412 ,  G11C11/419

Abstract: Certain aspects of the present disclosure are directed to a memory circuit. The memory circuit generally includes a memory cell coupled between a bit-line and a complementary bit-line. The memory circuit also includes a first n-type metal-oxide-semiconductor (NMOS) transistor configured to couple the bit-line to a write drive input during a write cycle of the memory circuit. The memory circuit also includes a second NMOS transistor configured to couple the complementary bit-line to a complementary write drive input during the write cycle, and a multiplexer circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between a voltage rail and the bit-line or the complementary bit-line, the multiplexer circuit being configured to couple, via the first PMOS transistor, the bit-line or the complementary bit-line to the voltage rail during the write cycle.

公开(公告)号：US10923185B2

公开(公告)日：2021-02-16

申请号：US16431639

申请日：2019-06-04

Applicant: QUALCOMM Incorporated

Inventor： Changho Jung ,  Keejong Kim ,  Chulmin Jung ,  Ritu Chaba

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/22 ,  G11C11/418 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10 ,  G11C7/12

Abstract: A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

公开(公告)号：US10796735B1

公开(公告)日：2020-10-06

申请号：US16459320

申请日：2019-07-01

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Keejong Kim ,  Anil Chowdary Kota ,  Chulmin Jung

IPC: G11C7/22 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C7/00 ,  G11C7/06

Abstract: In certain aspects, a memory device includes memory bit cells coupled to a read bit line, and a first sense amplifier having a first input coupled to the read bit line, and a first output. The memory device also includes a latch amplifier having a first input coupled to the first output of the first sense amplifier, an enable input, and an output. The memory device also includes one or more dummy bit cells coupled to a dummy bit line, and a second sense amplifier having a first input coupled to the dummy bit line, and an output. The memory device further includes a trigger circuit having an input coupled to the output of the second sense amplifier, and an output coupled to the enable input of the latch amplifier.

公开(公告)号：US10325648B2

公开(公告)日：2019-06-18

申请号：US15379285

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： Darshit Mehta ,  Chulmin Jung ,  Po-Hung Chen

IPC: G11C11/00 ,  G11C11/419 ,  G06F3/06 ,  G11C7/10

Abstract: The apparatus provided may be a memory circuit. The memory circuit includes a memory cell. The memory cell has a bitline. The memory circuit also includes a write driver. The write driver is configured to drive the bitline to write a bit to the memory cell during a write operation. The write driver is also configured to float the bitline to mask the bit during a read operation. The write driver may use NMOS pullup transistors.

公开(公告)号：US09916892B1

公开(公告)日：2018-03-13

申请号：US15448526

申请日：2017-03-02

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Mukund Narasimhan ,  Fahad Ahmed ,  Chulmin Jung

IPC: G11C11/419 ,  G11C5/14 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C7/12 ,  G11C11/412

Abstract: A pair of write driver inverters are arranged in series to drive a bit line responsive to a data bit input signal. A first boost capacitor provides a negative boost to a first ground node for a first one of the write driver inverters during the write assist period. A second boost capacitor provides a negative boost to a second ground node for a second one of the write driver inverters during the write assist period.