公开(公告)号：US20150194197A1

公开(公告)日：2015-07-09

申请号：US14591056

申请日：2015-01-07

Applicant: QUALCOMM Incorporated

Inventor： David Ian West ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  Vaishnav Srinivas

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G06F11/1004 ,  G06F11/1048 ,  G06F12/00 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

Abstract translation: 公开了动态随机存取存储器（DRAM）反向通道通信系统和方法。 在一个方面，反向通道通信系统允许DRAM将错误校正信息传送到片上系统（SoC），应用处理器（AP）或其他存储器控制器上来刷新警报信息。

公开(公告)号：US10140175B2

公开(公告)日：2018-11-27

申请号：US15081460

申请日：2016-03-25

Applicant: QUALCOMM Incorporated

Inventor： David Ian West ,  Jungwon Suh

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A memory sub-system may include a memory controller having error correction code (ECC) encoder/decoder logic. The memory controller may be configured to embed link ECC parity bits in unused data mask bits and/or in a mask write data during a mask write operation. The memory controller may also be configured to protect at least a location of the link ECC parity bits during the mask write operation.

公开(公告)号：US20170278554A1

公开(公告)日：2017-09-28

申请号：US15622772

申请日：2017-06-14

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G11C7/10 ,  G11C29/02

CPC classification number: G11C7/1072 ,  G11C29/022 ,  G11C29/028

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The signal is then returned to the SoC, where it may be examined by a closed-loop engine of the SoC. A result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

公开(公告)号：US09767868B2

公开(公告)日：2017-09-19

申请号：US14589145

申请日：2015-01-05

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G11C7/10 ,  G11C29/02

CPC classification number: G11C7/1072 ,  G11C29/022 ,  G11C29/028

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

公开(公告)号：US20150213850A1

公开(公告)日：2015-07-30

申请号：US14599768

申请日：2015-01-19

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  David Ian West

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/4243 ,  G06F13/4295 ,  Y02D10/14 ,  Y02D10/151

Abstract: Serial data transmission for dynamic random access memory (DRAM) interfaces is disclosed. Instead of the parallel data transmission that gives rise to skew concerns, exemplary aspects of the present disclosure transmit the bits of a word serially over a single lane of the bus. Because the bus is a high speed bus, even though the bits come in one after another (i.e., serially), the time between arrival of the first bit and arrival of the last bit of the word is still relatively short. Likewise, because the bits arrive serially, skew between bits becomes irrelevant. The bits are aggregated within a given amount of time and loaded into the memory array.

Abstract translation: 公开了用于动态随机存取存储器（DRAM）接口的串行数据传输。 代替引起偏斜关系的并行数据传输，本公开的示例性方面在总线的单个通道上串行地传送字的位。 由于总线是高速总线，即使这些位一个接一个地（即，串行地）进入，第一位到达之间的时间和该字的最后一位的到达仍然相对较短。 同样，由于这些位串行到达，所以位之间的偏移变得无关紧要。 这些位在给定的时间内聚合并加载到存储器阵列中。

公开(公告)号：US09965352B2

公开(公告)日：2018-05-08

申请号：US15151329

申请日：2016-05-10

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  David Ian West

IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G11C29/52

Abstract: A memory device may include link error correction code (ECC) decoder and correction circuitry. The ECC decoder and correction circuitry may be arranged in a write path and configured for link error detection and correction of write data received over a data link. The memory device may also include memory ECC encoder circuitry. The memory ECC encoder circuitry may be arranged in the write path and configured for memory protection of the write data during storage in a memory array.

公开(公告)号：US20180114553A1

公开(公告)日：2018-04-26

申请号：US15849463

申请日：2017-12-20

Applicant: QUALCOMM Incorporated

Inventor： David Ian West ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  Vaishnav Srinivas

IPC: G11C7/10 ,  G06F11/10 ,  G06F12/00 ,  G11C11/4076 ,  G11C11/406

CPC classification number: G11C7/1063 ,  G06F11/1004 ,  G06F11/1048 ,  G06F12/00 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

公开(公告)号：US09881656B2

公开(公告)日：2018-01-30

申请号：US14591056

申请日：2015-01-07

Applicant: QUALCOMM Incorporated

Inventor： David Ian West ,  Michael Joseph Brunolli ,  Dexter Tamio Chun ,  Vaishnav Srinivas

IPC: G11C7/10 ,  G06F11/10 ,  G11C11/406 ,  G06F12/00 ,  G11C11/4076

CPC classification number: G11C7/1063 ,  G06F11/1004 ,  G06F11/1048 ,  G06F12/00 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/4076

Abstract: Dynamic random access memory (DRAM) backchannel communication systems and methods are disclosed. In one aspect, a backchannel communication system allows a DRAM to communicate error correction information and refresh alert information to a System on a Chip (SoC), applications processor (AP), or other memory controller.

公开(公告)号：US09871012B2

公开(公告)日：2018-01-16

申请号：US13802759

申请日：2013-03-14

Applicant: QUALCOMM Incorporated

Inventor： Vaishnav Srinivas ,  Bernie Jord Yang ,  Michael Brunolli ,  David Ian West ,  Charles David Paynter

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/56

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L22/32 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/27 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/0556 ,  H01L2224/05569 ,  H01L2224/11462 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/14165 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/27462 ,  H01L2224/29028 ,  H01L2224/29078 ,  H01L2224/29147 ,  H01L2224/3012 ,  H01L2224/3213 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/381 ,  H01L2924/0105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.

公开(公告)号：US09281934B2

公开(公告)日：2016-03-08

申请号：US14268850

申请日：2014-05-02

Applicant: QUALCOMM Incorporated

Inventor： Yu Song ,  Jan Christian Diffenderfer ,  Nan Chen ,  David Ian West ,  Paul Lawrence Viani

IPC: H04L7/00 ,  H04L25/00 ,  H04L25/40 ,  H03L7/091 ,  H03L7/08 ,  H04L7/033

CPC classification number: H04L7/0016 ,  H03L7/0807 ,  H03L7/091 ,  H04L7/0083 ,  H04L7/0338

Abstract: Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.

Abstract translation: 公开了用于从数据输入信号恢复时钟和数据的系统和方法，用数据输入信号对多个时钟相位信号进行采样，以确定数据输入信号和时钟相位信号之间的定时关系，并使用确定的定时关系 选择一个时钟相位信号用于采样数据输入信号以产生恢复的数据。 CDR可以包括毛刺抑制模块，以抑制可能由数据输入信号上的大的瞬时抖动引起的时钟输出信号的毛刺。 使用这些方法的时钟和数据恢复电路（CDR）可以快速锁定到新的数据输入信号，并且可以在数据输入信号上存在大的瞬时定时抖动时可靠地接收数据。