公开(公告)号：US10089238B2

公开(公告)日：2018-10-02

申请号：US14334010

申请日：2014-07-17

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Palacharla ,  Moinul Khan ,  Alain Artieri ,  Kedar Bhole ,  Vinod Chamarty ,  Yanru Li ,  Raghu Sankuratri ,  George Patsilaras ,  Pavan Kumar Thirunagari ,  Andrew Edmund Turner ,  Jeong-Ho Woo

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/084 ,  G06F12/0895 ,  G06F9/50 ,  G06F12/0888 ,  G06F12/0864 ,  G06F1/32 ,  G06F17/30

Abstract: Aspects include computing devices, systems, and methods for dynamically partitioning a system cache by sets and ways into component caches. A system cache memory controller may manage the component caches and manage access to the component caches. The system cache memory controller may receive system cache access requests and reserve locations in the system cache corresponding to the component caches correlated with component cache identifiers of the requests. Reserving locations in the system cache may activate the locations in the system cache for use by a requesting client, and may also prevent other client from using the reserved locations in the system cache. Releasing the locations in the system cache may deactivate the locations in the system cache and allow other clients to use them. A client reserving locations in the system cache may change the amount of locations it has reserved within its component cache.

公开(公告)号：US20240428368A1

公开(公告)日：2024-12-26

申请号：US18338272

申请日：2023-06-20

Applicant: QUALCOMM Incorporated

Inventor： Vinay Thomas ,  David Berrebi ,  Victor Pinto ,  George Patsilaras ,  Roee Hardoon ,  Shruti Krishnamurthy ,  Weiliang Liu ,  Lingfeng Li ,  Alain Artieri ,  Abhilash Shivashankara Pillai

IPC: G06T1/60 ,  G06F12/0891

Abstract: This disclosure provides systems, methods, and devices for image signal processing that support efficient cache usage in an image processing system. In a first aspect, a method of image processing includes storing, by an image processor, a first portion of a first stripe of a first frame in a cache, the first portion of the first stripe overlapping a second portion of a second stripe of the first frame, reading, by the image processor, a third portion of the second stripe from a memory, reading, by the image processor, the first portion of the first stripe from the cache, and processing, by the image processor, the second stripe using the first portion of the first stripe and the third portion of the second stripe. Other aspects and features are also claimed and described.

公开(公告)号：US11016898B2

公开(公告)日：2021-05-25

申请号：US16543328

申请日：2019-08-16

Applicant: QUALCOMM INCORPORATED

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik ,  Wesley James Holland ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06F12/0868 ,  G06F12/02 ,  G06F12/0846 ,  G06F12/121 ,  G06F12/0891 ,  G06F12/0871 ,  G06F12/1072

Abstract: In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

公开(公告)号：US10747671B1

公开(公告)日：2020-08-18

申请号：US16269440

申请日：2019-02-06

Applicant: QUALCOMM INCORPORATED

Inventor： Wesley James Holland ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  George Patsilaras ,  Jeffrey Shabel ,  Simon Peter William Booth

IPC: G06T1/60 ,  G06F12/0862 ,  G06F12/1009

Abstract: An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

公开(公告)号：US10261910B2

公开(公告)日：2019-04-16

申请号：US15077534

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/0802 ,  G06F12/0875 ,  G06F12/0886

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

公开(公告)号：US09858196B2

公开(公告)日：2018-01-02

申请号：US14462773

申请日：2014-08-19

Applicant: QUALCOMM Incorporated

Inventor： George Patsilaras ,  Ali Iranli ,  Andrew Edmund Turner ,  Bohuslav Rychlik

IPC: G06F12/00 ,  G06F12/0893 ,  G06F12/0886 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0893 ,  G06F12/0886 ,  G06F2212/1028 ,  G06F2212/1044 ,  G06F2212/401 ,  Y02D10/13

Abstract: Aspects include computing devices, systems, and methods for implementing a cache memory access requests for data smaller than a cache line and eliminating overfetching from a main memory by combining the data with padding data of a size of a difference between a size of a cache line and the data. A processor may determine whether the data, uncompressed or compressed, is smaller than a cache line using a size of the data or a compression ratio of the data. The processor may generate the padding data using constant data values or a pattern of data values. The processor may send a write cache memory access request for the combined data to a cache memory controller, which may write the combined data to a cache memory. The cache memory controller may send a write memory access request to a memory controller, which may write the combined data to a memory.

公开(公告)号：US09489305B2

公开(公告)日：2016-11-08

申请号：US14571876

申请日：2014-12-16

Applicant: QUALCOMM INCORPORATED

Inventor： George Patsilaras ,  Bohuslav Rychlik ,  Andrew Edmund Turner ,  Kris Tiri ,  Jeong-Ho Woo ,  Anwar Rohillah ,  Feng Wang ,  Moinul Khan ,  Subbarao Palacharla

IPC: G06F12/00 ,  G06F12/08 ,  G06F1/32 ,  G06F13/16 ,  G06F9/46

CPC classification number: G06F12/0802 ,  G06F1/3253 ,  G06F9/467 ,  G06F12/0804 ,  G06F12/0835 ,  G06F12/0891 ,  G06F13/16 ,  G06F2212/604 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

Abstract translation: 公开了用于在芯片上的系统（“SoC”）中管理从主组件到长期存储器组件的写事务量的方法和系统的各种实施例。 因为当临时数据从紧密耦合的存储器组件（例如低级缓存“LLC”存储器））写入长期存储器（例如双倍数据速率“DDR”存储器）时，功耗和总线带宽被不必要地消耗 数据生成主组件，解决方案的实施例寻求识别包含短暂数据的写事务，并防止短暂数据被写入DDR。

公开(公告)号：US20160239344A1

公开(公告)日：2016-08-18

申请号：US14623554

申请日：2015-02-17

Applicant: QUALCOMM Incorporated

Inventor： Feng Wang ,  George Patsilaras

IPC: G06F9/50 ,  G06F12/08

CPC classification number: G06F9/5016 ,  G06F9/5044 ,  G06F9/5088 ,  G06F12/0811 ,  G06F12/084 ,  G06F2209/502 ,  G06F2209/505 ,  G06F2212/1024 ,  G06F2212/502

Abstract: Aspects include computing devices, systems, and methods for implementing scheduling an execution process to an execution processor cluster to take advantage of reduced latency with a victim cache. The computing device may determine a first processor cluster with a first remote shared cache memory having an available shared cache memory space. To properly schedule the execution process, the computing device may determine a second processor cluster with a lower latency to the first remote shared cache memory than an execution processor cluster scheduled with the execution process. The second processor cluster may be scheduled the execution process, thus becoming the execution processor cluster, based on a size of the available shared cache memory space and the latency of the second processor cluster to the first remote shared cache memory. The available shared cache memory space may be used as the victim cache for the execution process.

Abstract translation: 方面包括用于实现将执行过程调度到执行处理器集群以利用受害缓存的减少的延迟的计算设备，系统和方法。 计算设备可以使用具有可用共享高速缓冲存储器空间的第一远程共享高速缓冲存储器来确定第一处理器群集。 为了适当地安排执行过程，计算设备可以确定具有比执行处理调度的执行处理器群具有比第一远程共享高速缓冲存储器更低延迟的第二处理器群集。 可以基于可用的共享高速缓冲存储器空间的大小和第二处理器群集到第一远程共享高速缓冲存储器的等待时间来调度第二处理器群集，从而成为执行处理器群集。 可用的共享缓存存储器空间可以用作执行过程的受害缓存。

公开(公告)号：US09361228B2

公开(公告)日：2016-06-07

申请号：US14451639

申请日：2014-08-05

Applicant: QUALCOMM Incorporated

Inventor： Andrew Edmund Turner ,  George Patsilaras ,  Bohuslav Rychlik

IPC: G06F12/08

CPC classification number: G06F12/0875 ,  G06F12/0802 ,  G06F12/0886 ,  G06F2212/1021 ,  G06F2212/401 ,  G06F2212/45 ,  G06F2212/608

Abstract: Methods, devices, and non-transitory process-readable storage media for compacting data within cache lines of a cache. An aspect method may include identifying, by a processor of the computing device, a base address (e.g., a physical or virtual cache address) for a first data segment, identifying a data size (e.g., based on a compression ratio) for the first data segment, obtaining a base offset based on the identified data size and the base address of the first data segment, and calculating an offset address by offsetting the base address with the obtained base offset, wherein the calculated offset address is associated with a second data segment. In some aspects, the method may include identifying a parity value for the first data segment based on the base address and obtaining the base offset by performing a lookup on a stored table using the identified data size and identified parity value.

Abstract translation: 用于在高速缓存的高速缓存行中压缩数据的方法，设备和非暂态过程可读存储介质。 方面方法可以包括由计算设备的处理器识别用于第一数据段的基地址（例如，物理或虚拟高速缓存地址），识别第一数据段的数据大小（例如，基于压缩比） 数据段，基于所识别的数据大小和第一数据段的基址获得基本偏移，并且通过利用所获得的基本偏移量偏移基址来计算偏移地址，其中所计算的偏移地址与第二数据相关联 分割。 在一些方面，所述方法可以包括基于所述基地址识别所述第一数据段的奇偶校验值，并通过使用所识别的数据大小和所识别的奇偶校验值对存储的表执行查找来获得所述基本偏移。

公开(公告)号：US20240422335A1

公开(公告)日：2024-12-19

申请号：US18337109

申请日：2023-06-19

Applicant: QUALCOMM Incorporated

Inventor： Giwon Kim ,  Shengqi Yang ,  Younghoon Kim ,  George Patsilaras ,  Jaemoon Kim

IPC: H04N19/423 ,  H04N19/105 ,  H04N19/109 ,  H04N19/136 ,  H04N19/172 ,  H04N19/503

Abstract: A method includes generating a plurality of future reference picture lists associated with a plurality of future pictures of a set of pictures, wherein the set of pictures includes a current picture and the plurality of future pictures, and the plurality of future pictures follow the current picture in coding order, determining, based on information derived from the plurality of future reference picture lists associated with the plurality of future pictures, whether to write the current picture in a dedicated chip memory or whether to write the current picture in a non-dedicated system memory, and writing the current picture in the dedicated chip memory or the non-dedicated system memory based on the determination of whether to write the current picture in the dedicated chip memory or whether to write the current picture the non-dedicated system memory.