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    High density low power GSHE-STT MRAM
    11.
    发明授权
    High density low power GSHE-STT MRAM 有权
    高密度低功率GSHE-STT MRAM

    公开(公告)号：US09230627B2

    公开(公告)日：2016-01-05

    申请号：US14451510

    申请日：2014-08-05

    Applicant: QUALCOMM Incorporated

    Inventor： Wenqing Wu ,  Raghu Sagar Madala ,  Kendrick Hoy Leong Yuen ,  Karim Arabi

    IPC: G11C11/16 ,  H01L43/14 ,  G11C11/18

    CPC classification number: G11C11/161 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/18 ,  H01L43/14

    Abstract: Systems and methods are directed to a memory element comprising a hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) element, which includes a GSHE strip formed between a first terminal (A) and a second terminal (B), and a magnetic tunnel junction (MTJ), with a free layer of the MTJ interfacing the GSHE strip, and a fixed layer of the MTJ coupled to a third terminal (C). The orientation of the easy axis of the free layer is perpendicular to the magnetization created by electrons traversing the GSHE strip between the first terminal and the second terminal, such that the free layer of the MTJ is configured to switch based on a first charge current injected from/to the first terminal to/from the second terminal and a second charge current injected/extracted through the third terminal into/out of the MTJ via the third terminal (C).

    Abstract translation: 系统和方法涉及包括混合巨型旋转霍尔效应（GSHE） - 旋转转矩（STT）磁阻随机存取存储器（MRAM）元件的存储元件，其包括形成在第一端子（A）和第二端子 第二端子（B）和磁性隧道结（MTJ），具有与GSHE条带接合的MTJ的自由层和耦合到第三端子（C）的MTJ的固定层。 自由层的容易轴的取向垂直于通过在第一端子和第二端子之间穿过GSHE带的电子产生的磁化，使得MTJ的自由层被配置为基于注入的第一充电电流来切换 从第一端子到第二端子和从第二端子到第一端子的第二充电电流经由第三端子（C）通过第三端子注入/提取出MTJ的第二充电电流。

    CLOCK SKEW MANAGEMENT SYSTEMS, METHODS, AND RELATED COMPONENTS
    12.
    发明申请
    CLOCK SKEW MANAGEMENT SYSTEMS, METHODS, AND RELATED COMPONENTS 审中-公开

    公开(公告)号：US20150323958A1

    公开(公告)日：2015-11-12

    申请号：US14273061

    申请日：2014-05-08

    Applicant: QUALCOMM Incorporated

    Inventor： Karim Arabi

    IPC: G06F1/10

    CPC classification number: G06F1/10 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814

    Abstract: Clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary aspect, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use of automatic delay adjustment. In particular, a delay sensing circuit detects a difference in delay at comparable points in the clock tree between different tiers and instructs a programmable delay element to delay the clock signals on the faster of the two tiers. In a second exemplary aspect, a metal mesh is provided to all elements within the clock tree and acts as a signal aggregator that provides clock signals to the clocked elements substantially simultaneously.

    SYSTEM AND METHOD TO DESIGN AND TEST A YIELD SENSITIVE CIRCUIT
    13.
    发明申请
    SYSTEM AND METHOD TO DESIGN AND TEST A YIELD SENSITIVE CIRCUIT 有权
    设计和测试感应电路的系统和方法

    公开(公告)号：US20140223389A1

    公开(公告)日：2014-08-07

    申请号：US13757635

    申请日：2013-02-01

    Applicant: QUALCOMM INCORPORATED

    Inventor： Hongmei Liao ,  Karim Arabi

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G01R31/318558 ,  G06F11/267 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method includes identifying at least a portion of a design of a semiconductor device to be fabricated as a yield sensitive circuit. The method also includes, in response to identifying the yield sensitive circuit, forming a scan chain. Forming the scan chain includes inserting the yield sensitive circuit between a pair of flip flops and connecting the yield sensitive circuit to the pair of flip flops.

    Abstract translation: 一种方法包括将待制造的半导体器件的设计的至少一部分识别为屈服敏感电路。 该方法还包括响应于识别屈服敏感电路而形成扫描链。 形成扫描链包括将收益敏感电路插入一对触发器之间，并将收益敏感电路连接到一对触发器。

    Three-phase GSHE-MTJ non-volatile flip-flop
    14.
    发明授权
    Three-phase GSHE-MTJ non-volatile flip-flop 有权
    三相GSHE-MTJ非易失性触发器

    公开(公告)号：US09384812B2

    公开(公告)日：2016-07-05

    申请号：US14498336

    申请日：2014-09-26

    Applicant: QUALCOMM Incorporated

    Inventor： Wenqing Wu ,  Kendrick Hoy Leong Yuen ,  Karim Arabi

    IPC: G11C11/18 ,  G11C11/16 ,  H03K3/356 ,  H03K3/3562 ,  H03K3/45 ,  G11C11/155 ,  G11C14/00

    CPC classification number: G11C11/1693 ,  G11C11/155 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  G11C14/0081 ,  H03K3/356008 ,  H03K3/35625 ,  H03K3/45

    Abstract: Systems and methods are directed to a three-phase non-volatile flip-flop (NVFF), which includes a master stage formed from a dual giant spin Hall effect (GSHE)-magnetic tunnel junction (MTJ) structure, with a first GSHE-MTJ and a second GSHE-MTJ coupled between a first combined terminal and a second combined terminal, and a slave stage formed from a first inverter cross-coupled with a second inverter. A first data value is read out from the slave stage during a read phase of the same clock cycle that a second data value is written into the master stage during a write phase. The three-phase NVFF includes three control signals, for controlling an initialization phase of the slave stage, the read phase, and the write phase.

    Abstract translation: 系统和方法涉及三相非易失性触发器（NVFF），其包括由双巨型旋转霍尔效应（GSHE） - 磁性隧道结（MTJ）结构形成的主级，其具有第一GSHE- MTJ和耦合在第一组合终端和第二组合终端之间的第二GSHE-MTJ，以及由与第二逆变器交叉耦合的第一反相器形成的从级。 在写入阶段期间，将第二数据值写入主级的相同时钟周期的读取阶段，从从属级读出第一数据值。 三相NVFF包括三个控制信号，用于控制从站的初始化阶段，读取阶段和写入阶段。

    SPINTRONIC LOGIC GATES EMPLOYING A GIANT SPIN HALL EFFECT (GSHE) MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT(S) FOR PERFORMING LOGIC OPERATIONS, AND RELATED SYSTEMS AND METHODS
    16.
    发明申请
    SPINTRONIC LOGIC GATES EMPLOYING A GIANT SPIN HALL EFFECT (GSHE) MAGNETIC TUNNEL JUNCTION (MTJ) ELEMENT(S) FOR PERFORMING LOGIC OPERATIONS, AND RELATED SYSTEMS AND METHODS 审中-公开
    用于执行逻辑操作的巨型旋转霍尔效应（GSHE）磁通隧道（MTJ）元件的SPINTRONIC LOGIC GATES以及相关系统和方法

    公开(公告)号：US20150145575A1

    公开(公告)日：2015-05-28

    申请号：US14330494

    申请日：2014-07-14

    Applicant: QUALCOMM Incorporated

    Inventor： Wenqing Wu ,  Raghu Sagar Madala ,  Kendrick Hoy Leong Yuen ,  Karim Arabi ,  Robert Philip Gilmore

    IPC: H03K3/45 ,  H03K19/20 ,  H03K3/012 ,  H03K3/037

    CPC classification number: H03K3/45 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/18 ,  H01L43/08 ,  H03K19/18 ,  H03K19/20

    Abstract: Aspects described herein are related to spintronic logic gates employing a Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) element(s) for performing logical operations. In one aspect, a spintronic logic gate is disclosed that includes a charge current generation circuit and a GSHE MTJ element. The charge current generation circuit is configured to generate a charge current representing an input bit set. The input bit set may include one or more input bit states for a logical operation. The GSHE MTJ element is configured to set a logical output bit state for the logical operation, and has a threshold current level. The GSHE MTJ element is configured to generate a GSHE spin current in response to the charge current and perform the logical operation on the input bit set by setting the logical output bit state based on whether the GSHE spin current exceeds the threshold current level.

    Abstract translation: 本文描述的方面涉及采用用于执行逻辑操作的巨型旋转霍尔效应（GSHE）磁性隧道结（MTJ）元件的自旋电子逻辑门。 一方面，公开了一种包括充电电流产生电路和GSHE MTJ元件的自旋电子逻辑门。 充电电流产生电路被配置为产生表示输入位组的充电电流。 输入位集可以包括用于逻辑运算的一个或多个输入位状态。 GSHE MTJ元件配置为逻辑运算的逻辑输出位状态，并具有阈值电流电平。 GSHE MTJ元件被配置为响应于充电电流产生GSHE自旋电流，并且基于GSHE自旋电流是否超过阈值电流电平来设置逻辑输出位状态来对所设置的输入位执行逻辑运算。

    Hybrid scanning lidar systems
    17.
    发明授权
    Hybrid scanning lidar systems 有权

    公开(公告)号：US10534074B2

    公开(公告)日：2020-01-14

    申请号：US15253687

    申请日：2016-08-31

    Applicant: QUALCOMM Incorporated

    Inventor： Volodimir Slobodyanyuk ,  Matthew Grob ,  John Wyrwas ,  Karim Arabi ,  Rajesh Pankaj ,  Evgeni Gousev ,  Sajith Balraj

    IPC: G01S7/48 ,  G01S7/481 ,  G01S17/06

    Abstract: Disclosed herein are techniques for light beam scanning in a light detection and ranging (LIDAR) system. The LIDAR system includes a beam shaping subsystem configured to generate an illumination pattern elongated in a first direction, and a scanning subsystem configured to direct the elongated illumination pattern towards a plurality of positions along a second direction different from the first direction. The LIDAR system further includes a sensor configured to generate a detection signal in response to detecting light reflected by a target object illuminated by the elongated illumination pattern, and a processor configured to determine a characteristic of the target object based on the detection signal.

    Integrated circuit leakage power reduction using enhanced gated-Q scan techniques
    20.
    发明授权
    Integrated circuit leakage power reduction using enhanced gated-Q scan techniques 有权
    使用增强型门控Q扫描技术的集成电路泄漏功率降低

    公开(公告)号：US09584120B2

    公开(公告)日：2017-02-28

    申请号：US13887517

    申请日：2013-05-06

    Applicant: QUALCOMM Incorporated

    Inventor： Rajamani Sethuram ,  Karim Arabi

    IPC: H03K19/173 ,  H03K19/00 ,  G01R31/3183 ,  G01R31/3185 ,  G06F17/50

    CPC classification number: H03K19/0008 ,  G01R31/318342 ,  G01R31/318575 ,  G06F17/50 ,  H03K19/173

    Abstract: Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.

    Abstract translation: 通过确定电路设计的最小泄漏状态，然后选择将电路设计保持在其最低泄漏状态的逻辑门来选择用于Q门控的特定逻辑门。 根据实现最小泄漏状态所需的输入，栅极可以选择为NOR或或门。 在选择的操作模式期间可以启用用于实现最小泄漏状态的门实现的Q门控。 电路的最小泄漏状态可以用自动测试图形生成（ATPG）工具确定。

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