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    ANALOG-TO-DIGITAL CONVERTER, PHASE SAMPLER, TIME-TO-DIGITAL CONVERTER, AND FLIP-FLOP
    11.
    发明申请
    ANALOG-TO-DIGITAL CONVERTER, PHASE SAMPLER, TIME-TO-DIGITAL CONVERTER, AND FLIP-FLOP 有权

    公开(公告)号：US20220294433A1

    公开(公告)日：2022-09-15

    申请号：US17198515

    申请日：2021-03-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： Liang Dai ,  Kentaro Yamamoto ,  Behnam Sedighi

    IPC: H03K3/356 ,  H03M3/00

    Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

    Delta-sigma analog-to-digital converter (ADC) with time-interleaved (TI) or two-step successive approximation register (SAR) quantizer
    12.
    发明授权
    Delta-sigma analog-to-digital converter (ADC) with time-interleaved (TI) or two-step successive approximation register (SAR) quantizer 有权
    具有时间交织（TI）或两步逐次逼近寄存器（SAR）量化器的Delta-sigma模数转换器（ADC）

    公开(公告)号：US09455737B1

    公开(公告)日：2016-09-27

    申请号：US15049933

    申请日：2016-02-22

    Applicant: QUALCOMM Incorporated

    Inventor： Omid Rajaee ,  Changsok Han ,  Liang Dai ,  Seyed Arash Mirhaj ,  Ganesh Kiran

    IPC: H03M3/00

    CPC classification number: H03M3/464 ,  H03M1/1023 ,  H03M1/46 ,  H03M3/37 ,  H03M3/422 ,  H03M3/47

    Abstract: Certain aspects of the present disclosure provide a delta-sigma modulator (DSM) using time-interleaved (TI) successive approximation register (SAR) analog-to-digital converters (ADCs). For example, two SAR ADCs may be configured to alternately sample and process an input signal and provide a feedback signal for the DSM using excess loop delay (ELD). In other aspects, the DSM may be implemented using a two-step SAR quantizer. For example, a first SAR ADC may sample an input signal to generate a most-significant bit (MSB) portion of an output of the DSM, while the second SAR ADC may subsequently sample a residue from the first SAR ADC conversion and generate a least-significant bit (LSB) portion of the output of the DSM. With these techniques, higher bandwidths may be obtained in high accuracy delta-sigma ADCs without using increased sampling rates.

    Abstract translation: 本公开的某些方面提供了使用时间交织（TI）逐次逼近寄存器（SAR）模数转换器（ADC）的Δ-Σ调制器（DSM）。 例如，两个SAR ADC可以配置为交替采样和处理输入信号，并使用多余的环路延迟（ELD）为DSM提供反馈信号。 在其他方面，DSM可以使用两步SAR量化器来实现。 例如，第一SAR ADC可以采样输入信号以产生DSM的输出的最高有效位（MSB）部分，而第二SAR ADC可以随后从第一SAR ADC转换中采样残留，并产生最少 - DSM的输出的高位（LSB）部分。 利用这些技术，可以在高精度Δ-ΣADC中获得更高的带宽，而不使用提高的采样率。

    Analog-to-digital converter, phase sampler, time-to-digital converter, and flip-flop
    13.
    发明授权
    Analog-to-digital converter, phase sampler, time-to-digital converter, and flip-flop 有权

    公开(公告)号：US11476841B2

    公开(公告)日：2022-10-18

    申请号：US17198515

    申请日：2021-03-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： Liang Dai ,  Kentaro Yamamoto ,  Behnam Sedighi

    IPC: H03M1/00 ,  H03K3/356 ,  H03M3/00

    Abstract: A D-type flip-flop (DFF) includes an input circuit having a plurality of transistors configured to receive a clock signal and a data signal, a first inverter (INV1) having a pair of transistors, the first inverter configured to receive an input voltage (x) from the input circuit at a first inverter input, the first inverter configured to provide an output voltage (y) to a first inverter output, a second inverter (INV2) coupled to the first inverter (INV1), the second inverter having a second inverter input and a second inverter output, the second inverter input coupled to the first inverter output, a third inverter (INV3) coupled to the second inverter (INV2), the third inverter having a third inverter input and a third inverter output, and a current device coupled to the first inverter output, the current device configured to provide a current at the first inverter output.

    Time-to-digital converter (TDC)-based quantizer
    14.
    发明授权
    Time-to-digital converter (TDC)-based quantizer 有权

    公开(公告)号：US10044365B1

    公开(公告)日：2018-08-07

    申请号：US15843718

    申请日：2017-12-15

    Applicant: QUALCOMM Incorporated

    Inventor： Liang Dai ,  Kentaro Yamamoto ,  Omid Rajaee ,  Li Lu ,  Dinesh Alladi ,  Changsok Han

    IPC: H03M1/50 ,  H03L7/081 ,  H04W84/04 ,  H03M3/00

    Abstract: Certain aspects of the present disclosure provide apparatus and techniques for analog-to-digital conversion using a time-to-digital converter (TDC). For example, certain aspects provide a quantizer using a TDC. The quantizer may include at least one first capacitive element and a set of switches configured to selectively couple a first terminal and a second terminal of the at least one first capacitive element to at least one input voltage source. The TDC may also include a reference voltage source, at least one switch coupled between the second terminal of the at least one first capacitive element and an output of the reference voltage source, a current source selectively coupled to the first terminal of the at least one first capacitive element, and a voltage sense circuit coupled to the first terminal of the at least one first capacitive element.

    Noise shaping successive approximation register analog-to-digital converter
    18.
    发明授权
    Noise shaping successive approximation register analog-to-digital converter 有权
    噪声整形逐次逼近寄存器模数转换器

    公开(公告)号：US09425818B1

    公开(公告)日：2016-08-23

    申请号：US14724555

    申请日：2015-05-28

    Applicant: QUALCOMM Incorporated

    Inventor： Omid Rajaee ,  Dinesh Jagannath Alladi ,  Liang Dai

    IPC: H03M3/00

    CPC classification number: H03M3/426 ,  H03M1/466 ,  H03M3/32 ,  H03M3/436

    Abstract: An analog-to-digital converter includes: a first input terminal to receive a first input signal; a second input terminal to receive a second input signal; a noise shaping module configured to compare the first input signal to the second input signal received, and to output a digital output signal and a residue signal in a first phase of a noise shaping operation; and a storage module configured to store the residue signal during the first phase of the noise shaping operation, the storage module configured to receive an analog input signal and remove the residue signal from the analog input signal in a second phase of the noise shaping operation to output a new first input signal to the noise shaping module.

    Abstract translation: 模数转换器包括：第一输入端，用于接收第一输入信号; 第二输入端子，用于接收第二输入信号; 噪声整形模块，其被配置为将所述第一输入信号与所接收的所述第二输入信号进行比较，并且在噪声整形操作的第一阶段中输出数字输出信号和残留信号; 以及存储模块，被配置为在所述噪声整形操作的第一阶段期间存储所述残留信号，所述存储模块被配置为在所述噪声整形操作的第二阶段中接收模拟输入信号并从所述模拟输入信号中去除所述残留信号， 向噪声整形模块输出新的第一输入信号。

    Push-pull voltage driver with low static current variation
    19.
    发明授权
    Push-pull voltage driver with low static current variation 有权
    推挽电压驱动器具有低静态电流变化

    公开(公告)号：US09401707B1

    公开(公告)日：2016-07-26

    申请号：US14675936

    申请日：2015-04-01

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Song ,  Liang Dai

    IPC: H03K17/16

    CPC classification number: H03K17/165 ,  H03F1/0233 ,  H03F1/307 ,  H03F1/3217 ,  H03F3/26

    Abstract: A push-pull driver is provided with a differential amplifier that amplifies a difference between an input voltage and an output voltage to drive a bias node coupled to a diode-connected bias transistor. The push-pull driver is configured to control the drain-to-source voltage for a source-follower output transistor having its gate tied to a gate for the diode-connected bias transistor to be proportional to the drain-to-source voltage for the diode-connected bias transistor. This proportionality prevents excessive static current variation that would otherwise be present in the source-follower output transistor.

    Abstract translation: 推挽驱动器设置有差分放大器，其放大输入电压和输出电压之间的差以驱动耦合到二极管连接的偏置晶体管的偏置节点。 推挽驱动器被配置为控制源极跟随器输出晶体管的漏极 - 源极电压，其栅极连接到二极管连接的偏置晶体管的栅极与源极 - 源极电压成比例 二极管连接的偏置晶体管。 这种比例性可以防止在源极跟随器输出晶体管中存在的过大的静态电流变化。

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