公开(公告)号：US20220028758A1

公开(公告)日：2022-01-27

申请号：US16937426

申请日：2020-07-23

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Jonghae KIM ,  Periannan CHIDAMBARAM

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Disclosed is a semiconductor die with a through substrate via (TSV) structure having improved electrical characteristics suitable for backside power distribution networks (PDNs), and a method for making same. According to some aspects, a semiconductor die includes a substrate having a front side and a back side and includes a TSV extending from the back side of the substrate towards the front side of the substrate. The TSV includes a first portion extending from the back side of the substrate towards the front side of the substrate and having a first cross sectional area and a second portion extending from the first portion towards the front side of the substrate and having a second cross sectional area smaller than the first cross sectional area. A conductor is disposed within the TSV. According to some aspects, the first portion of the TSV is trench structure.

公开(公告)号：US20210118883A1

公开(公告)日：2021-04-22

申请号：US16654774

申请日：2019-10-16

Applicant: QUALCOMM Incorporated

Inventor： Kwanyong LIM ,  Stanley Seungchul SONG ,  Jun YUAN ,  Kern RIM

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L21/8238

Abstract: A device comprising a substrate and a first transistor formed over the substrate. The first transistor includes a first source disposed over the substrate, a first drain disposed over the substrate, a first plurality of channels coupled to the first source and the first drain, and a first gate surrounding the first plurality of channels. The first plurality of channels is located between the first source and the first drain. At least one channel includes silicon germanium (SiGe). The transistor is a field effect transistor (FET). The transistor is a gate all around (GAA) FET. The transistor may be configured to operate as a negative channel metal oxide semiconductor (NMOS) transistor. The transistor may be configured to operate as a positive channel metal oxide semiconductor (PMOS) transistor.

公开(公告)号：US20210057410A1

公开(公告)日：2021-02-25

申请号：US16817446

申请日：2020-03-12

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Hyunwoo PARK ,  Peijie FENG

IPC: H01L27/092 ,  H01L29/06

Abstract: An integrated device that includes a substrate, a first transistor, and a second transistor. The second transistor is configured to be coupled to the first transistor. The first transistor is configured to operate as a N-type channel metal oxide semiconductor transistor (NMOS) transistor. The first transistor includes a dielectric layer disposed over the substrate; a first source disposed over the dielectric layer; a first drain disposed over the dielectric layer; a first plurality of channels coupled to the first source and the first drain; and a first gate surrounding the plurality of channels. The second transistor is configured to operate as a P-type channel metal oxide semiconductor transistor (PMOS). The second transistor includes the dielectric layer; a second source disposed over the dielectric layer; a second drain disposed over the dielectric layer; a second plurality of channels coupled to the second source and the second drain; and a second gate.

公开(公告)号：US20180122824A1

公开(公告)日：2018-05-03

申请号：US15855996

申请日：2017-12-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul GUPTA ,  Xiangdong CHEN ,  Ohsang KWON ,  Foua VANG ,  Stanley Seungchul SONG ,  Kern RIM

IPC: H01L27/118 ,  H01L27/02 ,  H01L23/535 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.

公开(公告)号：US20170104088A1

公开(公告)日：2017-04-13

申请号：US15385811

申请日：2016-12-20

Applicant: QUALCOMM Incorporated

Inventor： Vladimir MACHKAOUTSAN ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Mustafa BADAROGLU ,  Choh Fei YEAP

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/225

CPC classification number: H01L29/66803 ,  H01L21/2254 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

公开(公告)号：US20160133634A1

公开(公告)日：2016-05-12

申请号：US14995195

申请日：2016-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Niladri Narayan MOJUMDER ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: H01L27/11 ,  H01L29/423 ,  H01L27/105

CPC classification number: H01L27/1052 ,  G11C11/412 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/785

Abstract: A complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell. A CMOS SRAM cell in accordance with an aspect of the present disclosure includes a bit line and a word line. Such a CMOS SRAM memory cell further includes a CMOS memory cell having at least a first p-channel device comprising a first channel material that differs from a substrate material of the CMOS memory cell, the first channel material having an intrinsic channel mobility greater than the intrinsic channel mobility of the substrate material, the first p-channel device coupling the CMOS memory cell to the bit line and the word line.

公开(公告)号：US20160071847A1

公开(公告)日：2016-03-10

申请号：US14480156

申请日：2014-09-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  Matthew Michael NOWAK ,  Choh Fei YEAP ,  Roawen CHEN

IPC: H01L27/088 ,  G06F17/50

CPC classification number: H01L27/0886 ,  G03F7/00 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0207

Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.

Abstract translation: 根据本公开的一个方面的用于半节点缩放电路布局的方法包括裸片上的垂直设备。 该方法包括降低管芯上的垂直装置的翅片间距和栅极间距。 该方法还包括缩放波长以限定电路布局的至少一个缩小区域几何图案。

公开(公告)号：US20160043092A1

公开(公告)日：2016-02-11

申请号：US14454805

申请日：2014-08-08

Applicant: QUALCOMM Incorporated

Inventor： Niladri Narayan MOJUMDER ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: H01L27/11

CPC classification number: H01L27/1052 ,  G11C11/412 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/785

Abstract: A complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell. A CMOS SRAM cell in accordance with an aspect of the present disclosure includes a bit line and a word line. Such a CMOS SRAM memory cell further includes a CMOS memory cell having at least a first p-channel device comprising a first channel material that differs from a substrate material of the CMOS memory cell, the first channel material having an intrinsic channel mobility greater than the intrinsic channel mobility of the substrate material, the first p-channel device coupling the CMOS memory cell to the bit line and the word line.

Abstract translation: 互补金属氧化物半导体（CMOS）静态随机存取存储器（SRAM）单元。 根据本公开的一个方面的CMOS SRAM单元包括位线和字线。 这种CMOS SRAM存储单元还包括具有至少第一p沟道器件的CMOS存储器单元，该第一p沟道器件包括与CMOS存储器单元的衬底材料不同的第一沟道材料，第一沟道材料具有大于 衬底材料的固有沟道迁移率，第一p沟道器件将CMOS存储器单元耦合到位线和字线。

公开(公告)号：US20160035891A1

公开(公告)日：2016-02-04

申请号：US14448548

申请日：2014-07-31

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Kern RIM ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/785

Abstract: A fin field-effect transistor (FinFET) includes a gate stack on a surface of a semiconductor fin. The semiconductor fin may include a capping material and a stressor material. The stressor material is confined by the capping material to a region proximate the gate stack. The stressor material provides stress on the semiconductor fin proximate the gate stack.

Abstract translation: 鳍状场效应晶体管（FinFET）包括在半导体鳍片的表面上的栅极堆叠。 半导体鳍片可以包括封盖材料和应力源材料。 应力源材料被封盖材料限制在靠近栅极叠层的区域。 应力源材料在靠近栅极堆叠的半导体鳍片上提供应力。

公开(公告)号：US20220020735A1

公开(公告)日：2022-01-20

申请号：US16928939

申请日：2020-07-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Jonghae KIM ,  Periannan CHIDAMBARAM ,  Pratyush KAMAL

IPC: H01L25/18 ,  H01L21/762 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00

Abstract: An integrated circuit (IC) package is described. The IC package includes a power delivery network. The IC package also includes a first die having a first surface and a second surface, opposite the first surface. The second surface is on a first surface of the power delivery network. The IC package further includes a second die having a first surface on the first surface of the first die. The IC package also includes package bumps on a second surface of the power delivery network, opposite the first surface of the power delivery network. The package bumps are coupled to contact pads of the power delivery network.