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    DIGITAL DESIGN WITH BUNDLED DATA ASYNCHRONOUS LOGIC AND BODY-BIASING TUNING
    12.
    发明申请
    DIGITAL DESIGN WITH BUNDLED DATA ASYNCHRONOUS LOGIC AND BODY-BIASING TUNING 审中-公开

    公开(公告)号：US20190213296A1

    公开(公告)日：2019-07-11

    申请号：US15866876

    申请日：2018-01-10

    Applicant: QUALCOMM Incorporated

    Inventor： Mark Lin ,  Yu Pu ,  Giby Samson

    IPC: G06F17/50

    Abstract: Aspects of the disclosure are directed to a digital design with bundled data asynchronous logic and body-biasing tuning. In one aspect, implementation includes establishing a control path between a first controller and a second controller using a handshaking protocol; establishing a data path between a first latch and a second latch using a bundled data technique; executing a first dynamic body biasing tuning by applying a first body bias signal to the control path; executing a second dynamic body biasing tuning by applying a second body bias signal to the data path. The digital design includes a first controller with a control path to connect to a second controller, wherein a first body bias tuning signal tunes body bias in the control path, a first latch with a data path to connect to a second latch, wherein a second body bias tuning signal tunes body bias in the data path.

    Clock distribution schemes with wide operating voltage ranges
    13.
    发明授权
    Clock distribution schemes with wide operating voltage ranges 有权

    公开(公告)号：US10050610B2

    公开(公告)日：2018-08-14

    申请号：US14642859

    申请日：2015-03-10

    Applicant: QUALCOMM Incorporated

    Inventor： Giby Samson ,  Yu Pu ,  Kendrick Hoy Leong Yuen

    IPC: G06F1/10 ,  H03K5/135 ,  H03K19/00 ,  H03K5/00

    Abstract: Clock distribution schemes with wide operating voltage ranges are disclosed. In one aspect, an operating voltage level or condition within a computing device is sensed. In a first voltage condition, delay elements are used within a clock tree to minimize clock skew. In a second voltage condition, one or more delay and/or clocked elements are bypassed to minimize clock skew at the second voltage condition. In addition to controlling clock skew, power may be conserved by depowering the bypassed elements. Controlling clock skew in this fashion improves operation of a computing device that includes the clock tree and may improve battery life.

    Techniques to identify a process corner
    18.
    发明授权
    Techniques to identify a process corner 有权

    公开(公告)号：US10191106B2

    公开(公告)日：2019-01-29

    申请号：US15015547

    申请日：2016-02-04

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Pu ,  Giby Samson ,  Kendrick Hoy Leong Yuen

    IPC: G01R31/02 ,  G01R31/28 ,  G01R31/30 ,  H01L21/66

    Abstract: Methods and apparatus for identifying a process corner are provided. Provided is an exemplary method for identifying a process corner of an integrated circuit (IC). The IC has a first asymmetrical ring oscillator (ARO1) including pull-up transistors that have a low threshold voltage (LVT) and pull-down transistors that have a regular threshold voltage (RVT), and has a second asymmetrical ring oscillator (ARO2) including pull-up transistors that have an RVT and pull-down transistors having an LVT. The exemplary method includes applying an ultra-low power supply voltage to the ARO1 and the ARO2 that causes the integrated circuit to operate near a verge of malfunction, measuring an output frequency of the ARO1, measuring an output frequency of the ARO2, calculating a calculated ratio of the output frequency of the ARO1 and the output frequency of the ARO2, and comparing the calculated ratio to a fiduciary ratio to identify the process corner.

    WEAR SENSOR AND METHOD OF OPERATION FOR A MEMORY DEVICE
    19.
    发明申请
    WEAR SENSOR AND METHOD OF OPERATION FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：US20180137929A1

    公开(公告)日：2018-05-17

    申请号：US15350669

    申请日：2016-11-14

    Applicant: QUALCOMM Incorporated

    Inventor： Giby Samson ,  Erik Hedberg ,  Francois Atallah ,  Keith Bowman

    IPC: G11C29/50 ,  G11C11/419

    CPC classification number: G11C29/50012 ,  G11C5/147 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028

    Abstract: A device includes a first set of storage elements, a second set of storage elements, and a bias circuit configured to generate a test bias signal to bias the first set of storage elements and the second set of storage elements. The device further includes a sensor circuit configured to receive a first signal from at least a first storage element of the first set of storage elements in response to the test bias signal and to receive a second signal from at least a second storage element of the second set of storage elements in response to the test bias signal. The sensor circuit is further configured to generate a third signal having a delay characteristic indicating a wear difference between the first storage element and the second storage element.

    ELECTRONIC DEVICES EMPLOYING ADIABATIC LOGIC CIRCUITS WITH WIRELESS CHARGING
    20.
    发明申请
    ELECTRONIC DEVICES EMPLOYING ADIABATIC LOGIC CIRCUITS WITH WIRELESS CHARGING 审中-公开

    公开(公告)号：US20180041210A1

    公开(公告)日：2018-02-08

    申请号：US15230885

    申请日：2016-08-08

    Applicant: QUALCOMM Incorporated

    Inventor： Yu Pu ,  Giby Samson

    IPC: H03K19/00 ,  H02J50/10 ,  H02J7/02

    CPC classification number: H03K19/0019 ,  H02J7/025 ,  H02J50/10 ,  H03K19/01707

    Abstract: Electronic devices employing adiabatic logic circuits with wireless charging are disclosed. In one aspect, an electronic device is provided. The electronic device includes a power circuit employing an alternating current (AC) coupler circuit configured to receive a wireless AC signal and generate a wired AC signal based on the wireless AC signal. The power circuit includes a power output configured to provide an AC power signal based on the wired AC signal generated by the AC coupler circuit. The AC power signal is generated based on the wireless charging capability of the AC coupler circuit. The electronic device employs a digital logic system that includes a power rail electrically coupled to an adiabatic logic circuit. The AC power signal is provided to the power rail to provide power to the adiabatic logic circuit. Wirelessly charging the adiabatic logic circuit consumes less power than conventional non-wireless charging circuitry.

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