公开(公告)号：US20150333004A1

公开(公告)日：2015-11-19

申请号：US14276763

申请日：2014-05-13

Applicant: QUALCOMM Incorporated

Inventor： Houssam Wafic JOMAA ,  Omar James BCHIR ,  Kuiwon KANG ,  Chin-Kwan KIM

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.

Abstract translation: 提供了用光电介质材料形成半导体衬底的方法和装置，嵌入迹线，延伸穿过两个电介质层的无衬垫跳过和无芯封装。 在一个实施例中，一种形成具有铜层的芯的方法; 将铜层层压成光电介质层; 在光电介质层中形成多个迹线图案; 电镀所述多个迹线图案以形成多个迹线; 在光电介质层上形成绝缘介电层; 通过绝缘介电层和光电介质层形成通孔; 在所述绝缘介电层上形成额外的布线图案; 去除核心; 并施加焊接掩模。

公开(公告)号：US20240373561A1

公开(公告)日：2024-11-07

申请号：US18310324

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Jung Won PARK ,  Kuiwon KANG ,  Seongryul CHOI

IPC: H05K1/18 ,  H05K3/28

Abstract: In an aspect, an electronic device is disclosed that includes a substrate comprising a core having an upper planar surface and a lower planar surface, wherein the core includes a cavity extending between the upper planar surface of the core and the lower planar surface of the core; an electronic component at least partially disposed in the cavity, wherein the electronic component is at least partially surrounded in the cavity by a cured plugging ink, the electronic component including an upper planar surface having one or more electronic component terminals; and an upper metallization structure configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

公开(公告)号：US20240371737A1

公开(公告)日：2024-11-07

申请号：US18310425

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Joan Rey Villarba BUOT ,  Michelle Yejin KIM ,  Kuiwon KANG

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: In an aspect, an electronic device is disclosed that includes a substrate comprising a core having an upper planar surface and a lower planar surface, wherein the core includes a cavity extending through the core; an electronic component at least partially disposed in the cavity, wherein the electronic component has an upper planar surface having one or more electronic component terminals; a first cured resin layer, wherein the upper planar surface of the electronic component is at least partially embedded in the first cured resin layer at least at an upper portion of the cavity; and an upper metallization structure disposed over the upper planar surface of the core, wherein the upper metallization structure is configured to provide one or more conductive paths from the one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

公开(公告)号：US20230352390A1

公开(公告)日：2023-11-02

申请号：US17735075

申请日：2022-05-02

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  Joan Rey Villarba BUOT ,  Zhijie WANG ,  Marcus HSU ,  Sang-Jae LEE ,  Kuiwon KANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L21/4857 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L24/32 ,  H01L2224/32237 ,  H01L24/73 ,  H01L2224/73204 ,  H01L24/83 ,  H01L2224/83192 ,  H01L2224/81815 ,  H01L2224/81203 ,  H01L2224/81385 ,  H01L23/49822

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a bump pad interconnect. The bump pad interconnect comprises a profile cross section that has a trapezoid shape. The integrated device is coupled to the substrate through the bump pad interconnect. The bump pad interconnect is located in a cavity of the at least one dielectric layer of the substrate.

公开(公告)号：US20220384328A1

公开(公告)日：2022-12-01

申请号：US17334610

申请日：2021-05-28

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Hong Bok WE ,  Chin-Kwan KIM ,  Milind SHAH

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.

公开(公告)号：US20210175178A1

公开(公告)日：2021-06-10

申请号：US16704378

申请日：2019-12-05

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Aniket PATIL ,  Kuiwon KANG ,  Zhijie WANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A package comprising a first integrated device, a first encapsulation layer, a redistribution portion, a second integrated device and an encapsulation layer. The first encapsulation layer encapsulates the first integrated device. The redistribution portion includes a plurality of redistribution interconnects. The redistribution portion includes a first surface and a second surface. The first integrated device and the first encapsulation layer are coupled to the first surface of the redistribution portion. The second integrated device is coupled to the second surface of the redistribution portion. The second encapsulation layer is coupled to the second surface of the redistribution portion such that the second encapsulation layer encapsulates the second integrated device.

公开(公告)号：US20210057397A1

公开(公告)日：2021-02-25

申请号：US16546158

申请日：2019-08-20

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Seongryul CHOI ,  Haekyun KIM

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/13 ,  H01L23/00 ,  H01L21/48

Abstract: An electronic assembly is disclosed that includes an electrodeless passive component embedded in a cavity of a multilayer substrate, wherein the cavity has conductive elements formed on at least two sidewalls of the cavity. The conductive elements are configured to be electrically coupled to the electrodeless passive component. The electrodeless passive component may be located in a first metal layer adjacent an external surface of the multilayer substrate.

公开(公告)号：US20200176417A1

公开(公告)日：2020-06-04

申请号：US16209723

申请日：2018-12-04

Applicant: QUALCOMM Incorporated

Inventor： Brigham NAVAJA ,  Yue LI ,  Kuiwon KANG ,  Soumyadipta BASU ,  Joan Rey Villarba BUOT

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/64 ,  H01L23/00 ,  H05K1/18

Abstract: The present disclosure generally relates to an integrated circuit having a stacked embedded passive substrate (EPS) structure formed therein. In particular, a substrate may have a cavity formed therein and the stacked EPS structure may include multiple passive components formed in the cavity to provide separate electrical paths for decoupling of the integrated circuit. Furthermore, the multiple passive components may each have two respective terminals such that the multiple passive components may support different voltage domains. Among other things, compared to conventional die-side and/or land-side passive components, the stacked EPS structure may advantageously reduce a z-axis height of the integrated circuit, reduce manufacturing costs, improve performance due to shorter electrical paths, and improve design routing through x-axis and y-axis space savings.

公开(公告)号：US20180323137A1

公开(公告)日：2018-11-08

申请号：US15678698

申请日：2017-08-16

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Houssam JOMAA ,  Layal ROUHANA ,  Seongryul CHOI

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5384

Abstract: A device comprising a semiconductor die, a package substrate coupled to the semiconductor die, and an encapsulation layer that at least partially encapsulates the semiconductor die. The package substrate includes at least one stacked via. The at least one stacked via includes a first via and a second via coupled to the first via. The second via includes a seed layer coupled to the first via. The second via includes a different shape than the first via. The package substrate includes a prepreg layer. The package substrate includes a first pad coupled to the first via, and a second pad coupled to the second via.

公开(公告)号：US20250069965A1

公开(公告)日：2025-02-27

申请号：US18456295

申请日：2023-08-25

Applicant: QUALCOMM Incorporated

Inventor： Ryan LANE ,  Charles David PAYNTER ,  William STONE ,  Ahmer SYED ,  Yue LI ,  Kuiwon KANG ,  Wei WANG ,  Durodami LISK

IPC: H01L23/13 ,  H01L23/00

Abstract: A package comprising an integrated device and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate comprises at least one dielectric layer; a frame at least partially located in the at least one dielectric layer; and a plurality of interconnects located at least partially in the at least one dielectric layer. The frame may be an embedded frame.