公开(公告)号：US20240339414A1

公开(公告)日：2024-10-10

申请号：US18296843

申请日：2023-04-06

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun YEON ,  Suhyung HWANG ,  Omar James BCHIR ,  Hyunchul CHO ,  Yeoil PARK

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: A hybrid core substrate with embedded components, and methods for making the same, are disclosed. In an aspect a hybrid core substrate comprises a rigid core, a first laminate layer structure disposed above and mounted to the top surface of the rigid core and having a cavity in which a first component is embedded, and a second laminate layer structure disposed above and mounted to a top surface of the first laminate layer structure and having at least one electrical connection to the first laminate layer structure and at least one electrical connection to the first component, a first plurality of contacts disposed on the top surface of the second laminate layer structure and electrically connected to the second laminate layer structure. In some aspects, at least one contact is electrically connected to the embedded component.

公开(公告)号：US20160183386A1

公开(公告)日：2016-06-23

申请号：US14617864

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Young Kyu SONG ,  Layal ROUHANA ,  Kyu-Pyung HWANG ,  Omar James BCHIR

IPC: H05K3/46 ,  H05K3/32 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K3/4644 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0231 ,  H05K1/0234 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/113 ,  H05K1/114 ,  H05K1/115 ,  H05K1/167 ,  H05K1/181 ,  H05K3/1258 ,  H05K3/321 ,  H05K3/3442 ,  H05K3/4697 ,  H05K2201/0792 ,  H05K2201/09227 ,  H05K2201/09281 ,  H05K2201/09954 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2203/0545 ,  Y02P70/611

Abstract: Methods and apparatus for controlling an equivalent-series resistance (ESR) of a capacitor are provided. An exemplary apparatus includes a substrate having a land side, the capacitor mounted on the land side of the substrate and having both the ESR and terminals, a resistive pattern coupled to the terminals, and a plurality of vias coupled to the resistive pattern. The resistive pattern is configured to control the ESR. The resistive pattern can be formed of a resistive paste. The resistive pattern can be formed in a substantially semicircular shape having an arc ranging from substantially 45 degrees to substantially 135 degrees. The capacitor can be a surface mount device. The resistive pattern can be formed in a shape of a land-side capacitor mounting pad, a via, or both.

Abstract translation: 提供了用于控制电容器的等效串联电阻（ESR）的方法和装置。 示例性装置包括具有接地侧的基板，安装在基板的接地侧上并具有ESR和端子的电容器，耦合到端子的电阻图案以及耦合到电阻图案的多个通孔。 电阻模式被配置为控制ESR。 电阻图案可以由电阻浆料形成。 电阻图案可以形成为具有大致45度至基本上135度的弧度的大致半圆形状。 电容器可以是表面贴装器件。 电阻图案可以形成为陆侧电容器安装垫，通孔或两者的形状。

公开(公告)号：US20160093567A1

公开(公告)日：2016-03-31

申请号：US14498397

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  Rajneesh KUMAR ,  Layal ROUHANA ,  Joan Rey V. BUOT ,  Omar James BCHIR

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76834 ,  H01L21/76898 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5223 ,  H01L23/5389 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15333 ,  H01L2924/19041 ,  H01L2924/19106

Abstract: A semiconductor substrate according to some examples of the disclosure may include a substrate with a cavity in a top surface of the substrate, a plurality of cavity interconnections embedded below a bottom surface of the cavity and extending to a bottom surface of the substrate, and a plurality of side interconnections to either side of the cavity extending from the top surface of the substrate to the bottom surface of the substrate. Each of the plurality of side interconnections may include an electrically conductive stop etch layer in the same horizontal plane as the bottom of the cavity.

Abstract translation: 根据本公开的一些示例的半导体衬底可以包括在衬底的顶表面中具有空腔的衬底，多个腔互连嵌入在腔的底表面下方并延伸到衬底的底表面，并且 多个侧面互连到空腔的任一侧，从衬底的顶表面延伸到衬底的底表面。 多个侧面互连中的每一个可以包括在与空腔的底部相同的水平平面中的导电停止蚀刻层。

公开(公告)号：US20160218064A1

公开(公告)日：2016-07-28

申请号：US14603166

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan KIM ,  David Fraser RAE ,  Rajneesh KUMAR ,  Milind Pravin SHAH ,  Omar James BCHIR

IPC: H01L23/538 ,  H01L25/16 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.

Abstract translation: 半导体封装可以包括具有附接到其表面的一个或多个电子部件的下基板和具有一个或多个空腔的上基板，其中上基板在与一个或多个电子元件的多个连接点处附接到下基板 装配在单个空腔内的部件或用于允许半导体封装的整体形状保持较小的每个部件的单独的腔体。 多个连接点在上基板和下基板之间提供机械和电连接，并且可以包括在其之间的焊接接头以及当被压缩以组装时产生粘合剂增强矩阵的导电填料颗粒。

公开(公告)号：US20160163443A1

公开(公告)日：2016-06-09

申请号：US14743623

申请日：2015-06-18

Applicant: QUALCOMM Incorporated

Inventor： Mete ERTURK ,  Ravindra Vaman SHENOY ,  Kwan-yu LAI ,  Jitae KIM ,  Donald William KIDWELL JR. ,  Jon Bradley LASITER ,  James Thomas DOYLE ,  Omar James BCHIR

IPC: H01F27/28 ,  H01F41/14 ,  H05K1/18 ,  H01F41/02 ,  H05K1/11 ,  H01F27/24 ,  H01F1/147

CPC classification number: H01F27/2804 ,  H01F1/14708 ,  H01F5/00 ,  H01F17/0033 ,  H01F27/24 ,  H01F41/02 ,  H01F41/046 ,  H01F41/14 ,  H01F2017/002 ,  H01F2017/0066 ,  H01F2027/2809 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/645 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/111 ,  H05K1/165 ,  H05K1/182 ,  H05K2201/10166 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor can include a first substrate, a magnetic piece, and a conductor. The first substrate can be formed within a second substrate. The magnetic piece can be connected to a first side of the first substrate. The conductor can be formed within the second substrate, on the second substrate, or both. The conductor can have an input and an output. The conductor can be configured to surround the first substrate without being in contact with the first substrate and without being in contact with the magnetic piece.

Abstract translation: 电感器可以包括第一衬底，磁片和导体。 第一基板可以形成在第二基板内。 磁片可以连接到第一衬底的第一侧。 导体可以形成在第二基板内，第二基板上，或两者上。 导体可以具有输入和输出。 导体可以被配置为围绕第一基板而不与第一基板接触并且不与磁片接触。

公开(公告)号：US20150333004A1

公开(公告)日：2015-11-19

申请号：US14276763

申请日：2014-05-13

Applicant: QUALCOMM Incorporated

Inventor： Houssam Wafic JOMAA ,  Omar James BCHIR ,  Kuiwon KANG ,  Chin-Kwan KIM

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.

Abstract translation: 提供了用光电介质材料形成半导体衬底的方法和装置，嵌入迹线，延伸穿过两个电介质层的无衬垫跳过和无芯封装。 在一个实施例中，一种形成具有铜层的芯的方法; 将铜层层压成光电介质层; 在光电介质层中形成多个迹线图案; 电镀所述多个迹线图案以形成多个迹线; 在光电介质层上形成绝缘介电层; 通过绝缘介电层和光电介质层形成通孔; 在所述绝缘介电层上形成额外的布线图案; 去除核心; 并施加焊接掩模。