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公开(公告)号：US20150358008A1
公开(公告)日：2015-12-10
申请号：US14300119
申请日：2014-06-09
Applicant: Qualcomm Incorporated
Inventor： Li Sun , Zhi Zhu , Xiaohua Kong
CPC classification number: H03K5/13 , H03K2005/00052 , H03K2005/00286 , H04L7/0025 , H04L7/02
Abstract: A phase interpolator, including: a pair of load resistors coupled to a supply voltage; a plurality of branches coupled to the pair of load resistors, each branch including a differential pair of transistors connected at source terminal to form a source node; a plurality of tail current sources, each tail current source coupled to one of the source nodes; and a plurality of coupling capacitors, each coupling capacitor coupled between the source nodes in two adjacent branches of the plurality of branches.
Abstract translation: 一种相位插值器，包括：耦合到电源电压的一对负载电阻; 耦合到所述一对负载电阻器的多个分支，每个分支包括在源极端子处连接以形成源节点的差分对晶体管; 多个尾流源，每个尾电流源耦合到源节点之一; 以及多个耦合电容器，每个耦合电容器耦合在所述多个分支的两个相邻分支中的源节点之间。
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12.发明申请Linearity of Phase Interpolators by Combining Current Coding and Size Coding 有权通过组合当前编码和大小编码的相位插值器的线性度公开(公告)号：US20150358148A1
公开(公告)日：2015-12-10
申请号：US14300127
申请日：2014-06-09
Applicant: Qualcomm Incorporated
Inventor： Li Sun , Zhi Zhu , Xiaohua Kong , Kenneth Luis Arcudia , Zhiqin Chen
CPC classification number: H04L7/0331 , H03K5/135 , H03K2005/00065 , H03L7/099
Abstract: A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.
Abstract translation: 一种相位插值器，包括：包括第一多个分支和多个尾电流源的第一部分，每个分支包括差分对晶体管，所述差分对晶体管的源极端子连接以形成源节点，其中每个尾部 电流源耦合到源节点之一，并且其中所述差分对晶体管和相应的尾电流源以当前编码方案配置; 第二部分包括第二多个分支和耦合到第二多个分支的固定电流源，第二多个分支的每个分支包括第二多个差分对晶体管和多个开关，其以尺寸编码方案 ; 其中所述第一部分和所述第二部分彼此耦合并耦合到一对负载电阻器。
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公开(公告)号：US20150303910A1
公开(公告)日：2015-10-22
申请号：US14258980
申请日：2014-04-22
Applicant: QUALCOMM Incorporated
Inventor： Zhi Zhu , Xiaohua Kong , Li Sun , Jie Xu
IPC: H03K9/08
CPC classification number: H03K9/08 , G06F13/4072 , H04L25/4902 , Y02D10/14 , Y02D10/151
Abstract: Systems and methods for decoding pulse-width modulated (PWM) data are disclosed. An example decoder filters a data input signal with a one-sided pulse filter. The one-sided pulse filter suppresses short pulses on the data input signal and passes long pulses. The example decoder latch the filtered data signal at the end of each bit time of the data input signal. The duration of pulses that are suppressed by the one-sided pulse filter can be calibrated to compensate for circuit variations and to allow the decoder to operate at various data rates. The decoder can be implemented in a small integrated circuit area and can be power efficient.
Abstract translation: 公开了用于解码脉宽调制（PWM）数据的系统和方法。 示例解码器用单向脉冲滤波器对数据输入信号进行滤波。 单面脉冲滤波器抑制数据输入信号的短脉冲，并通过长脉冲。 示例解码器在数据输入信号的每个位时间结束时锁存经滤波的数据信号。 由单侧脉冲滤波器抑制的脉冲的持续时间可被校准，以补偿电路变化并允许解码器以各种数据速率工作。 解码器可以在小的集成电路区域中实现，并且可以是功率效率的。
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公开(公告)号：US11469730B2
公开(公告)日：2022-10-11
申请号：US17099183
申请日：2020-11-16
Applicant: QUALCOMM Incorporated
Abstract: A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.
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公开(公告)号：US10992277B1
公开(公告)日：2021-04-27
申请号：US16785464
申请日：2020-02-07
Applicant: QUALCOMM Incorporated
Inventor： Li Sun , Dong Ren , Hao Liu , Sudheer Chowdary Gali
Abstract: Certain aspects are directed to an amplifier. The amplifier generally includes a first transistor having a gate coupled to an input node of the amplifier, a source degeneration circuit, and a second transistor coupled between the source degeneration circuit and a source of the first transistor, a gate of the second transistor being configured to receive a gain control signal from a controller.
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Patent Agency Ranking
公开(公告)号：US10698439B1
公开(公告)日：2020-06-30
申请号：US16413292
申请日：2019-05-15
Applicant: QUALCOMM Incorporated
Inventor： Li Sun , Russell Deans , Zhiqin Chen , Zhi Zhu
Abstract: In certain aspects, an apparatus includes a multiplexer having a first input, a second input, a select input, and an output, wherein the first input is configured to receive a first reference clock signal, the second input is configured to receive a second reference clock signal, and the select input is configured to receive a select signal. The multiplexer is configured to select one of the first and second reference clock signals based on the select signal, and output the selected one of the first and second reference clock signals at the output of the multiplexer. The apparatus also includes a clock driver having an input and an output, wherein the input of the clock driver is coupled to the output of the multiplexer.
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公开(公告)号：US09755817B2
公开(公告)日：2017-09-05
申请号：US15013914
申请日：2016-02-02
Applicant: QUALCOMM Incorporated
Inventor： Eskinder Hailu , Hanan Cohen , Li Sun , Zhiqin Chen
Abstract: A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated output signal. In response to a high-resolution signal, at least one of the slices may switch on both the first switch and the second switch.
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公开(公告)号：US10972108B1
公开(公告)日：2021-04-06
申请号：US16864652
申请日：2020-05-01
Applicant: QUALCOMM Incorporated
Abstract: A clock system including: an in-phase clock input and an in-phase clock output; a quadrature clock input and a quadrature clock output; a control loop configured to receive the in-phase clock output and the quadrature clock output, the control loop including a Boolean logic gate coupled to an operational amplifier (op-amp) through a low-pass filter; and an analog delay element coupled between the quadrature clock input and the quadrature clock output, the analog delay element comprising a plurality of capacitors.
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公开(公告)号：US20180219704A1
公开(公告)日：2018-08-02
申请号：US15422050
申请日：2017-02-01
Applicant: QUALCOMM Incorporated
Inventor： Yu Song , Zhi Zhu , Miao Li , Li Sun , Deqiang Song , Chia Heng Chang
CPC classification number: H04L25/03273 , H03L7/0814 , H04L7/0025 , H04L7/0337 , H04L43/16 , H04L2027/0069
Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).
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公开(公告)号：US20170222789A1
公开(公告)日：2017-08-03
申请号：US15013914
申请日：2016-02-02
Applicant: QUALCOMM Incorporated
Inventor： Eskinder Hailu , Hanan Cohen , Li Sun , Zhiqin Chen
IPC: H04L7/00
Abstract: A phase interpolator is provided with a plurality of slices. Each slice includes a first switch for mixing a first clock signal into an interpolated output signal and a second switch for mixing a second clock signal into the interpolated output signal. In response to a high-resolution signal, at least one of the slices may switch on both the first switch and the second switch.
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