公开(公告)号：US09762237B1

公开(公告)日：2017-09-12

申请号：US15192921

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Patrick Isakanian

IPC: H03B1/00 ,  H03K19/00 ,  H03K17/687 ,  G11C11/4074 ,  G11C11/408

CPC classification number: H03K19/0005 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4087 ,  H03K17/687 ,  H03K19/018507 ,  H03K19/018557 ,  H03K19/018585

Abstract: A transmitter is provided with a plurality of pull-up legs and a plurality of pull-down legs. A controller controls the pull-up legs and the pull-down legs so that a constant output impedance is provided while supporting a range of logic-high output voltages.

公开(公告)号：US20170090546A1

公开(公告)日：2017-03-30

申请号：US14863890

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Michael Brunolli ,  Stephen Thilenius ,  Patrick Isakanian ,  Vaishnav Srinivas

IPC: G06F1/32 ,  G11C11/4074 ,  G11C7/10

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3209 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/16 ,  G06F13/4086 ,  G06F13/4243 ,  G11C7/1072 ,  G11C11/4074 ,  H04L25/0278 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.

公开(公告)号：US20160269017A1

公开(公告)日：2016-09-15

申请号：US14812516

申请日：2015-07-29

Applicant: QUALCOMM Incorporated

Inventor： Alvin Leng Sun Loke ,  Bo Yu ,  Stephen Clifford Thilenius ,  Reza Jalilizeinali ,  Patrick Isakanian

IPC: H03K17/082

CPC classification number: H03K17/0822 ,  H03K19/00315 ,  H03K19/018521

Abstract: An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.

Abstract translation: 提供电子电路和操作电子电路的方法。 电子电路包括用于将输出电路的输入/输出（I / O）节点提升到第一电压的上拉晶体管和用于将上拉晶体管耦合到I / O节点的第一隔离晶体管。 电子电路还包括用于将I / O节点下拉到第二电压的下拉晶体管和用于将下拉晶体管耦合到I / O节点的第二隔离晶体管。 在电子电路中，上拉和下拉晶体管是支持第一漏极 - 源极电压和第一栅极 - 源极电压的晶体管，而第一和第二隔离晶体管是支撑第一漏极 并且第二栅极至源极电压大于第一栅极至源极电压。