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公开(公告)号：US08922245B2
公开(公告)日：2014-12-30
申请号：US13963122
申请日：2013-08-09
Applicant: Rambus Inc.
Inventor： Kyung Suk Oh , Chi-Ming Yeung , David A. Secker
IPC: H03K3/012 , G11C7/10 , H04L25/02 , G11C11/4074
CPC classification number: H03K3/012 , G11C7/1057 , G11C11/4074 , H04L25/028
Abstract: In an asymmetrically terminated communication system, the power consumed to transmit a particular bit value is adjusted based on whether the bit being output is the second, third, fourth, etc. consecutive bit with the same value after a transition to output the particular bit value. The adjustment of the power consumed to transmit the two or more consecutive bits with the same value may be made by adjusting the driver strength during the second, or subsequent, consecutive bits with the same value. The adjustment of the power consumed is performed on the bit value that consumes the most DC power and the other value is typically not adjusted.
Abstract translation: 在不对称端接的通信系统中，基于输出位是否是具有相同值的第二，第三，第四等等的连续位，在输出特定位值之后，调整发送特定位值所消耗的功率 。 可以通过在具有相同值的第二个或后续的连续位中调整驱动器强度来进行用于传送具有相同值的两个或更多个连续位的消耗的功率的调整。 消耗功率的调整是对消耗最多DC功率的比特值进行的，另一个值通常不被调整。
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公开(公告)号：US12147367B2
公开(公告)日：2024-11-19
申请号：US18355660
申请日：2023-07-20
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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公开(公告)号：US12142348B2
公开(公告)日：2024-11-12
申请号：US18460413
申请日：2023-09-01
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Lawrence Lai , Fan Ho , David A. Secker , Wayne S. Richardson , Akash Bansal , Brian S. Leibowitz , Kyung Suk Oh
Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
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公开(公告)号：US11783879B2
公开(公告)日：2023-10-10
申请号：US17531151
申请日：2021-11-19
Applicant: Rambus Inc.
Inventor： Ian Shaeffer , Lawrence Lai , Fan Ho , David A. Secker , Wayne S. Richardson , Akash Bansal , Brian S. Leibowitz , Kyung Suk Oh
CPC classification number: G11C8/12 , G11C5/02 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1012 , G11C7/1045 , G11C8/18 , H01L24/49 , H01L25/0657 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48095 , H01L2224/48227 , H01L2224/48471 , H01L2224/49171 , H01L2224/49433 , H01L2224/73265 , H01L2225/0651 , H01L2924/00012 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/15311 , H01L2224/73265 , H01L2224/32225 , H01L2224/48227 , H01L2924/00012 , H01L2224/73265 , H01L2224/32145 , H01L2224/48227 , H01L2924/00012 , H01L2224/48095 , H01L2924/00014 , H01L2924/00014 , H01L2224/45099 , H01L2224/49171 , H01L2224/48227 , H01L2924/00 , H01L2224/49171 , H01L2224/48471 , H01L2924/00 , H01L2224/49171 , H01L2224/49433 , H01L2924/00 , H01L2924/181 , H01L2924/00012
Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
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公开(公告)号：US20230138512A1
公开(公告)日：2023-05-04
申请号：US17989838
申请日：2022-11-18
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
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Patent Agency Ranking
公开(公告)号：US20210124703A1
公开(公告)日：2021-04-29
申请号：US16950861
申请日：2020-11-17
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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公开(公告)号：US20250103531A1
公开(公告)日：2025-03-27
申请号：US18919179
申请日：2024-10-17
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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公开(公告)号：US20240220141A1
公开(公告)日：2024-07-04
申请号：US18419933
申请日：2024-01-23
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
CPC classification number: G06F3/0635 , G06F3/0613 , G06F3/0656 , G06F3/0673 , G06F13/1678 , Y02D10/00
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
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公开(公告)号：US11907555B2
公开(公告)日：2024-02-20
申请号：US17989838
申请日：2022-11-18
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
CPC classification number: G06F3/0635 , G06F3/0613 , G06F3/0656 , G06F3/0673 , G06F13/1678 , Y02D10/00
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
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公开(公告)号：US11755521B2
公开(公告)日：2023-09-12
申请号：US17809688
申请日：2022-06-29
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Suresh Rajan , Ravindranath Kollipara , Ian Shaeffer , David A. Secker
CPC classification number: G06F13/4022 , G06F12/00 , G06F13/00 , G06F13/1673 , G06F13/1694
Abstract: A memory module comprises a data interface including a plurality of data lines and a plurality of configurable switches coupled between the data interface and a data path to one or more memories. The effective width of the memory module can be configured by enabling or disabling different subsets of the configurable switches. The configurable switches may be controlled by manual switches, by a buffer on the memory module, by an external memory controller, or by the memories on the memory module.
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