公开(公告)号：US20160042812A1

公开(公告)日：2016-02-11

申请号：US14918148

申请日：2015-10-20

Applicant: RAMBUS INC.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/12 ,  G11C11/401

CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Abstract translation: 控制器包括用于存储地址的内部存储器和与内部存储器可操作地耦合的存储器控​​制单元。 存储器控制单元包括用于识别外部存储器件内的主要数据存储元件的故障地址的逻辑，外部存储器件是与控制器分离的另一个半导体器件，将故障地址存储在内部存储器中，并传输到外部存储器 存储器装置，使用冗余数据存储元件发起故障地址的修复的命令以及与故障地址相关联的地址的指示。

公开(公告)号：US09129712B2

公开(公告)日：2015-09-08

申请号：US14150659

申请日：2014-01-08

Applicant: RAMBUS INC.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/48 ,  G11C29/44

CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

Abstract: A controller including a non-volatile memory to store a repair address, and a memory control unit operatively coupled with the non-volatile memory. The memory control unit comprising a memory test function configured to detect a malfunctioning address of primary data storage elements within a memory device. The memory device being another semiconductor device separate from the controller. The memory test function configured to store the repair address in the non-volatile memory, the repair address indicating the malfunctioning address of the primary data storage element.

Abstract translation: 一种包括用于存储修复地址的非易失性存储器的控制器，以及与非易失性存储器可操作地耦合的存储器控​​制单元。 存储器控制单元包括存储器测试功能，其被配置为检测存储器设备内主要数据存储元件的故障地址。 存储器件是与控制器分开的另一个半导体器件。 所述存储器测试功能被配置为将所述修复地址存储在所述非易失性存储器中，所述修复地址指示所述主数据存储元件的故障地址。

公开(公告)号：US20200273534A1

公开(公告)日：2020-08-27

申请号：US16870759

申请日：2020-05-08

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

公开(公告)号：US20190027231A1

公开(公告)日：2019-01-24

申请号：US16015941

申请日：2018-06-22

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C11/408 ,  G11C29/48 ,  G11C11/401 ,  G11C29/12 ,  G11C29/04 ,  G11C29/02

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

公开(公告)号：US20180047436A1

公开(公告)日：2018-02-15

申请号：US15623261

申请日：2017-06-14

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C5/04 ,  G11C5/06 ,  G11C8/18 ,  H01L23/00 ,  H01L25/065 ,  G11C5/02 ,  G11C7/10

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US09378849B2

公开(公告)日：2016-06-28

申请号：US14918148

申请日：2015-10-20

Applicant: RAMBUS INC.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12

CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/789 ,  G11C29/802 ,  G11C2229/743

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.

Abstract translation: 控制器包括用于存储地址的内部存储器和与内部存储器可操作地耦合的存储器控​​制单元。 存储器控制单元包括用于识别外部存储器件内的主要数据存储元件的故障地址的逻辑，外部存储器件是与控制器分离的另一个半导体器件，将故障地址存储在内部存储器中，并传输到外部存储器 存储器装置，使用冗余数据存储元件发起故障地址的修复的命令以及与故障地址相关联的地址的指示。

公开(公告)号：US20150332746A1

公开(公告)日：2015-11-19

申请号：US14813028

申请日：2015-07-29

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C8/18 ,  G11C5/02

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract translation: 描述了包括可编程命令和地址（CA）接口和/或可编程数据接口的存储器件。 在操作模式下，两个或多个CA接口可能处于活动状态。 在另一操作模式中，至少一个但不是全部的CA接口可能是活动的。 在操作模式下，所有数据接口都可能处于活动状态。 在另一种操作模式中，至少一个但不是全部的数据接口可能是活动的。 存储器装置可以包括用于选择：操作模式的电路; 操作模式中的子模式; 一个或多个CA接口作为活动CA接口; 来自多个活动CA接口的主CA接口; 和/或一个或多个数据接口作为活动数据接口。 电路可以基于一个或多个寄存器中的一个或多个位和/或在一个或多个引脚上接收到的一个或多个信号来执行这些选择。

公开(公告)号：US20130194854A1

公开(公告)日：2013-08-01

申请号：US13753360

申请日：2013-01-29

Applicant: RAMBUS INC.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C5/06

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US11783910B2

公开(公告)日：2023-10-10

申请号：US17720054

申请日：2022-04-13

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

CPC classification number: G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/802 ,  G11C29/789 ,  G11C2229/743

Abstract: A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

公开(公告)号：US20210407619A1

公开(公告)日：2021-12-30

申请号：US17344155

申请日：2021-06-10

Applicant: Rambus Inc.

Inventor： Adrian E. Ong ,  Fan Ho

IPC: G11C29/00 ,  G11C29/44 ,  G11C29/48 ,  G11C29/04 ,  G11C11/401 ,  G11C29/12 ,  G11C11/408 ,  G11C29/02

Abstract: A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.