-
公开(公告)号：US20130342240A1
公开(公告)日：2013-12-26
申请号：US13915290
申请日：2013-06-11
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Kambiz Kaviani , Aliazam Abbasfar
IPC: H03K5/24
CPC classification number: H04L25/03949 , H03K5/24
Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.
-
公开(公告)号：US11340686B2
公开(公告)日：2022-05-24
申请号：US16947973
申请日：2020-08-26
Applicant: Rambus Inc.
Inventor： Dinesh Patil , Amir Amirkhany , Farrukh Aquil , Kambiz Kaviani , Frederick A. Ware
IPC: G06F1/324 , G11C7/10 , G11C7/22 , G11C11/4093 , G11C11/4076 , G06F1/3234 , G06F1/3287 , G06F5/06 , G11C7/04 , H03L7/081
Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
-
公开(公告)号：US09571034B2
公开(公告)日：2017-02-14
申请号：US15049517
申请日：2016-02-22
Applicant: Rambus Inc.
Inventor： Mohammad Hekmat , Farshid Aryanfar , Kambiz Kaviani
CPC classification number: H03B27/00 , H01F27/006 , H01F27/2804 , H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B15/00 , H03K5/145 , H03K5/24 , H03K2005/00052
Abstract: Coupled multi-inductors and their applications. An apparatus includes several circuit stages. Each circuit stage includes an inductive element that overlaps with the inductive elements of its adjacent circuit stages, forming a loop of coupled circuit stages. The apparatus may be, for example, a multi-phase oscillator with multiple oscillators that are magnetically coupled to each other for generating oscillation signals at different phases. The apparatus may also be, for example, a phase interpolator for combining input signals.
Abstract translation: 耦合多电感及其应用。 一种装置包括几个电路级。 每个电路级包括与其相邻电路级的电感元件重叠的电感元件，形成耦合电路级的回路。 该装置可以是例如具有彼此磁耦合的多个振荡器的多相振荡器，用于在不同相位产生振荡信号。 该装置也可以是例如用于组合输入信号的相位插值器。
-
公开(公告)号：US09515856B2
公开(公告)日：2016-12-06
申请号：US14720518
申请日：2015-05-22
Applicant: Rambus Inc.
Inventor： Kambiz Kaviani , Amir Amirkhany , Jason Chia-Jen Wei , Aliazam Abbasfar
CPC classification number: H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
Abstract: A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.
-
15.发明授权公开(公告)号：US09389637B2
公开(公告)日：2016-07-12
申请号：US13867954
申请日：2013-04-22
Applicant: Rambus Inc.
Inventor： Huy Nguyen , Vijay Gadde , Kambiz Kaviani , Thomas Giovannini , Todd Bystrom
IPC: G06F1/12
CPC classification number: G06F1/12
Abstract: A source-synchronous communication system in which a first integrated circuit (IC) conveys a data signal and concomitant strobe signal to a second IC. One or both ICs support hysteresis for the strobe channel that allows the second IC to distinguish between strobe preambles and noise, and thus prevent the false triggering of data capture. Hysteresis may also be employed to quickly settle the strobe channel to an inactive level after receipt of a strobe postamble.
Abstract translation: 一种源同步通信系统，其中第一集成电路（IC）向第二IC传送数据信号和伴随选通信号。 一个或两个IC支持选通通道的滞后，允许第二IC区分选通前导和噪声，从而防止数据捕获的错误触发。 还可以采用迟滞来在接收到选通后同步码之后快速地将频闪通道置于非活动状态。
-
Patent Agency Ranking
公开(公告)号：US09166838B1
公开(公告)日：2015-10-20
申请号：US14489814
申请日：2014-09-18
Applicant: Rambus Inc.
Inventor： Lei Luo , Barry W. Daly , Kambiz Kaviani , John Cronan Eble, III , John Wilson
CPC classification number: H03K3/013 , G11C5/147 , G11C29/021 , G11C29/022 , G11C29/028 , H04L25/0296 , H04L25/06 , H04L25/08
Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.
Abstract translation: 发射机上的信号以与电源的正节点分离的方式跟踪接地节点上的噪声。 信号从发射机发射到接收机。 在接收机上产生参考电压以跟踪接收机中接地节点上的噪声。 因此，接收信号和参考电压具有基本上相同的噪声特性，这些噪声特性成为当这两个信号彼此进行比较时可以消除的共模噪声。 在另一实施例中，将参考电压与预定校准图案进行比较。 基于采样器输出和预定校准图案之间的差异产生误差信号。 然后使用误差信号来调整参考电压，使得参考电压的直流电平基本上位于接收信号的中间。
-
17.发明申请PARTIAL RESPONSE DECISION FEEDBACK EQUALIZER WITH SELECTION CIRCUITRY HAVING HOLD STATE 有权具有选举电路的部分反应决定反馈平衡器公开(公告)号：US20150103876A1
公开(公告)日：2015-04-16
申请号：US14575985
申请日：2014-12-18
Applicant: Rambus Inc.
Inventor： Amir Amirkhany , Kambiz Kaviani , Aliazam Abbasfar
IPC: H04L25/03
CPC classification number: H04L25/03949 , H03K5/24
Abstract: A partial response decision feedback equalizer (PrDFE) includes a receiver including at least first and second comparators operative to compare an input signal representing a sequence of symbols against respective thresholds and to respectively generate first and second receiver outputs. A first selection stage is provided to select (a) between the first comparator output and a first resolved symbol according to a first timing signal, and (b) between the second comparator output and the first resolved symbol according to the first timing signal, to produce respective first and second selection outputs. A second selection stage selects between the first and second selection outputs according to a selection signal. The selection signal is dependent on a prior resolved symbol that precedes the first resolved symbol in the sequence.
Abstract translation: 部分响应判决反馈均衡器（PrDFE）包括至少包括第一和第二比较器的接收器，该第一和第二比较器可操作以将表示符号序列的输入信号与相应阈值进行比较，并且分别产生第一和第二接收器输出。 提供第一选择级，以根据第一定时信号在第一比较器输出和第一解析符号之间选择（a），以及（b）根据第一定时信号在第二比较器输出和第一解析符号之间选择 产生相应的第一和第二选择输出。 第二选择阶段根据选择信号在第一和第二选择输出之间进行选择。 选择信号取决于序列中第一个已解析符号之前的先前解析符号。
-
公开(公告)号：US08933729B1
公开(公告)日：2015-01-13
申请号：US13834970
申请日：2013-03-15
Applicant: Rambus Inc.
Inventor： Xudong Shi , Reza Navid , Jason Chia-Jen Wei , Huy M. Nguyen , Kambiz Kaviani
CPC classification number: H03K5/00 , H03F3/195 , H03F3/45179 , H03F3/45654 , H03F3/68 , H03F2203/45418 , H03F2203/45424 , H03F2203/45498 , H03F2203/45702 , H04L25/0276
Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.
Abstract translation: 差分接收器“堆叠”，并独立校准到不同的共模电压。 不同的共模电压可以对应于堆叠的发送电路的共模电压。 多个采样器堆叠连接到相同的通道。 每个采样器电路堆的时钟被定时（定时），使得给定堆栈中的采样器不能同时解析。 在不同的堆叠中并且接收不同共模电压的采样器同时解析。
-
公开(公告)号：US20240345646A1
公开(公告)日：2024-10-17
申请号：US18643714
申请日：2024-04-23
Applicant: Rambus Inc.
Inventor： Dinesh Patil , Amir Amirkhany , Farrukh Aquil , Kambiz Kaviani , Frederick A. Ware
IPC: G06F1/324 , G06F1/3234 , G06F1/3287 , G06F5/06 , G11C7/04 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093 , H03L7/081
CPC classification number: G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G06F2205/067 , G11C7/04 , G11C2207/2272 , H03L7/0816
Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
-
公开(公告)号：US11994930B2
公开(公告)日：2024-05-28
申请号：US17748704
申请日：2022-05-19
Applicant: Rambus Inc.
Inventor： Dinesh Patil , Amir Amirkhany , Farrukh Aquil , Kambiz Kaviani , Frederick A. Ware
IPC: G06F1/324 , G06F1/3234 , G06F1/3287 , G06F5/06 , G11C7/10 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C7/04 , H03L7/081
CPC classification number: G06F1/324 , G06F1/3275 , G06F1/3287 , G06F5/065 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4076 , G11C11/4093 , G06F2205/067 , G11C7/04 , G11C2207/2272 , H03L7/0816
Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.
-
-
-
-
-
-
-
-
-
Search Results
36
records
(took 0.02 seconds)
