公开(公告)号：US20200013857A1

公开(公告)日：2020-01-09

申请号：US16575836

申请日：2019-09-19

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20180226431A1

公开(公告)日：2018-08-09

申请号：US15942754

申请日：2018-04-02

Applicant: Renesas Electronics Corporation

Inventor： Hideki MAKIYAMA

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/76283 ,  H01L21/84 ,  H01L29/0649

Abstract: Reliability of a semiconductor device is improved. Prepared is a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed by using a first etching liquid; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned by using a second etching liquid different from the first etching liquid. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed. An etching speed of each of the insulating film and the insulating layer due to the first etching liquid is smaller than an etching speed of the semiconductor layer by using the first etching liquid. An etching speed of each of the insulating film and the insulating layer due to a second etching liquid is higher than the etching speed of each of the insulating film and the insulating layer due to the first etching liquid.

公开(公告)号：US20170222013A1

公开(公告)日：2017-08-03

申请号：US15361037

申请日：2016-11-24

Applicant: Renesas Electronics Corporation

Inventor： Hideki MAKIYAMA

IPC: H01L29/49 ,  H01L21/311 ,  H01L21/66 ,  H01L23/522 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L27/12 ,  H01L21/84 ,  H01L21/265

CPC classification number: H01L29/4983 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/265 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/84 ,  H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L23/5226 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The thickness of an insulating film, which will serve as an offset spacer film and is formed in an offset monitor region, is managed as the thickness of an offset spacer film formed over the side wall surface of a gate electrode of an SOTB transistor STR, etc. When the measured thickness is within the tolerance of a standard thickness, standard implantation energy and a standard dose amount are set. When the measured thickness is smaller than the standard thickness, implantation energy and a dose amount, which are respectively lower than the standard values thereof, are set. When the measured thickness is larger than the standard thickness, implantation energy and a dose amount, which are respectively higher than the standard values thereof, are set.

公开(公告)号：US20160181147A1

公开(公告)日：2016-06-23

申请号：US15054696

申请日：2016-02-26

Applicant: Renesas Electronics Corporation

Inventor： Jiro YUGAMI ,  Toshiaki IWAMATSU ,  Katsuyuki HORITA ,  Hideki MAKIYAMA ,  Yasuo INOUE ,  Yoshiki YAMAMOTO

IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/30604 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649

Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.

公开(公告)号：US20140375379A1

公开(公告)日：2014-12-25

申请号：US14310731

申请日：2014-06-20

Applicant: Renesas Electronics Corporation

Inventor： Hideki MAKIYAMA ,  Toshiaki IWAMATSU

IPC: G05F1/625

CPC classification number: H03K17/687 ,  G05F1/625 ,  H01L27/1203 ,  H01L29/78 ,  H03K2217/0018

Abstract: A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined.

Abstract translation: 作为电流监视电路，半导体集成电路器件具有其中n沟道型MISFET彼此串联连接的电路。 基于将衬底偏压施加到p沟道型MISFET的状态下的速度监视器电路的延迟时间，确定要施加到p沟道型MISFET的第一衬底偏置的第一电压值。 接下来，基于在第一衬底偏压被施加到电流监视电路的p沟道型MISFET的状态下流过n沟道型MISFET的电流，并且第二衬底偏置被施加到n沟道 确定要施加到n沟道型MISFET的第二衬底偏置的第二电压值。

公开(公告)号：US20230011018A1

公开(公告)日：2023-01-12

申请号：US17369643

申请日：2021-07-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki MAKIYAMA

IPC: H01L21/02 ,  H01L21/762

Abstract: A wafer having a semiconductor substrate including a peripheral region and a central region, an insulating layer and a semiconductor layer is prepared first. Next, a plurality of trenches penetrating through the semiconductor layer and the insulating layer and reaching an inside of the semiconductor substrate are formed. Next, an inside of each of the plurality of trenches is filled with an insulating film, so that a plurality of element isolating portions is formed. Next, in the central region, the semiconductor layer exposed from a resist pattern is removed. The end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for removing the semiconductor layer in the central region is formed so as to be positioned closer to the outer edge of the semiconductor substrate than a position of the end portion closest to the outer edge of the semiconductor substrate among ends of the resist pattern used for forming the trenches.

公开(公告)号：US20210257459A1

公开(公告)日：2021-08-19

申请号：US17224743

申请日：2021-04-07

Applicant: Renesas Electronics Corporation

Inventor： Yoshiki YAMAMOTO ,  Hideki MAKIYAMA ,  Toshiaki IWAMATSU ,  Takaaki TSUNOMURA

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/265 ,  H01L29/06 ,  H01L21/74 ,  H01L21/8234

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented.
A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

公开(公告)号：US20180350844A1

公开(公告)日：2018-12-06

申请号：US16040305

申请日：2018-07-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki MAKIYAMA ,  Yoshiki YAMAMOTO

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L27/1207 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/42356 ,  H01L29/66545

Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.

公开(公告)号：US20170062624A1

公开(公告)日：2017-03-02

申请号：US15201493

申请日：2016-07-03

Applicant: Renesas Electronics Corporation

Inventor： Hideki MAKIYAMA

IPC: H01L29/792 ,  H01L27/115 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/0649 ,  H01L29/0852 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/7838

Abstract: Performances of a semiconductor device are improved. The semiconductor device has: a gate electrode formed on an SOI layer of an SOI substrate via a gate insulating film having a charge storage film therein; an n-type semiconductor region and a p-type semiconductor region respectively formed on SOI layers on both sides of the gate electrode. A memory cell MC serving as a non-volatile memory cell is formed of the gate insulating film, the gate electrode, the n-type semiconductor region and the p-type semiconductor region.

Abstract translation: 提高了半导体器件的性能。 半导体器件具有：通过其中具有电荷存储膜的栅极绝缘膜形成在SOI衬底的SOI层上的栅电极; 分别形成在栅电极两侧的SOI层上的n型半导体区域和p型半导体区域。 用作非易失性存储单元的存储单元MC由栅极绝缘膜，栅极电极，n型半导体区域和p型半导体区域形成。

公开(公告)号：US20160043717A1

公开(公告)日：2016-02-11

申请号：US14919644

申请日：2015-10-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideki MAKIYAMA ,  Toshiaki IWAMATSU

IPC: H03K17/687 ,  H01L27/12

CPC classification number: H03K17/687 ,  G05F1/625 ,  H01L27/1203 ,  H01L29/78 ,  H03K2217/0018

Abstract: A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined.

Abstract translation: 作为电流监视电路，半导体集成电路器件具有其中n沟道型MISFET彼此串联连接的电路。 基于将衬底偏压施加到p沟道型MISFET的状态下的速度监视器电路的延迟时间，确定要施加到p沟道型MISFET的第一衬底偏置的第一电压值。 接下来，基于在第一衬底偏压被施加到电流监视电路的p沟道型MISFET的状态下流过n沟道型MISFET的电流，并且第二衬底偏置被施加到n沟道 确定要施加到n沟道型MISFET的第二衬底偏置的第二电压值。