公开(公告)号：US20190148518A1

公开(公告)日：2019-05-16

申请号：US16116633

申请日：2018-08-29

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L29/66 ,  H01L27/11573

Abstract: A semiconductor device in which the retention characteristics of a rewritable memory cell packaged together with a field effect transistor including a metal gate electrode are improved and a method for manufacturing the semiconductor device. The semiconductor device includes a field effect transistor with a metal gate electrode and a rewritable memory cell. The manufacturing method includes the step of replacing a dummy gate electrode with the metal gate electrode. Before the step of replacing the dummy gate electrode with the metal gate electrode, the method includes the steps of making the height of the memory cell lower than the height of the dummy gate electrode and forming a protective film for covering the memory cell.

公开(公告)号：US20180047723A1

公开(公告)日：2018-02-15

申请号：US15792009

申请日：2017-10-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/06 ,  H01L29/66 ,  G11C16/04 ,  H01L29/792

CPC classification number: H01L27/0629 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  H01L21/823468 ,  H01L27/1104 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The improvement of the reliability of a semiconductor device having a split gate type MONOS memory is implemented. An ONO film and a second polysilicon film are sequentially formed so as to fill between a first polysilicon film and a dummy gate electrode. Then, the dummy gate electrode is removed. Then, the top surfaces of the first and second polysilicon films are polished, thereby to form a memory gate electrode formed of the second polysilicon film at the sidewall of a control gate electrode formed of the first polysilicon film via the ONO film. As a result, the memory gate electrode high in perpendicularity of the sidewall, and uniform in film thickness is formed.

公开(公告)号：US20170287924A1

公开(公告)日：2017-10-05

申请号：US15623547

申请日：2017-06-15

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/11568 ,  H01L29/423 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42376 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7853 ,  H01L29/7855 ,  H01L29/792 ,  H01L29/7923

Abstract: A fin includes a first region and a second region arranged on a positive side in an X-axis direction with respect to the first region. A control gate electrode covers an upper surface of the first region, and a side surface of the first region on the positive side in a Y-axis direction. A memory gate electrode covers an upper surface of the second region, and a side surface of the second region on the positive side in the Y-axis direction. The upper surface of the second region is lower than the upper surface of the first region. The side surface of the second region is arranged on the negative side in the Y-axis direction with respect to the side surface of the first region in the Y-axis direction.

公开(公告)号：US20170207233A1

公开(公告)日：2017-07-20

申请号：US15473568

申请日：2017-03-29

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA ,  Masaaki SHINOHARA

IPC: H01L27/11568 ,  H01L29/66 ,  H01L27/11573 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L21/28282 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

Abstract: The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, a first insulation film, a conductive film, a silicon-containing second insulation film, and a third film formed of silicon are sequentially formed at the surface of a control gate electrode. Then, the third film is etched back to leave the third film at the side surface of the control gate electrode via the first insulation film, the conductive film, and the second insulation film, thereby to form a spacer. Then, the conductive film is etched back to form a memory gate electrode formed of the conductive film between the spacer and the control gate electrode, and between the spacer and the semiconductor substrate.

公开(公告)号：US20160293738A1

公开(公告)日：2016-10-06

申请号：US15017612

申请日：2016-02-06

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L27/115 ,  H01L29/08

CPC classification number: H01L29/66833 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/6653

Abstract: An improvement is made in the reliability of a semiconductor device having a split gate type MONOS memory. An ONO film covering a control gate electrode, and a dummy memory electrode gates are formed, and then a diffusion region on a source-region-side of a memory to produced is formed across the dummy memory electrode gates. Subsequently, the dummy memory electrode gates is removed, and then a memory gate electrode is formed which is smaller in gate length than the dummy memory electrode gates. Thereafter, an extension region on the source-region-side of the memory is formed.

Abstract translation: 具有分离栅型MONOS存储器的半导体器件的可靠性得到改进。 形成覆盖控制栅电极的ONO膜和虚设存储电极栅极，然后在伪存储电极栅极之间形成在要产生的存储器的源极区侧的扩散区域。 随后，去除虚拟存储器电极栅极，然后形成栅极长度比虚拟存储器电极栅极小的存储栅电极。 此后，形成存储器的源极 - 区域侧上的延伸区域。

公开(公告)号：US20150087128A1

公开(公告)日：2015-03-26

申请号：US14560437

申请日：2014-12-04

Applicant: Renesas Electronics Corporation

Inventor： Koji MAEKAWA ,  Tatsuyoshi MIHARA

IPC: H01L29/66

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/0615 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66553 ,  Y10S257/90 ,  Y10S438/90

Abstract: An insulating film and another insulating film are formed over a semiconductor substrate in that order to cover first, second, and third gate electrodes. The another insulating film is etched back to form sidewall spacers over side surfaces of the insulating film. Then, the sidewall spacers over the side surfaces of the insulating films corresponding to the sidewalls of the first and second gate electrodes are removed to leave the sidewall spacers over the side surfaces of the insulating film corresponding to the sidewalls of the third gate electrode. Then, the sidewall spacers and the insulating films are etched back, so that the sidewall spacers are formed of the insulating film over the sidewalls of the first, second, and third gate electrodes.

Abstract translation: 为了覆盖第一，第二和第三栅电极，在半导体衬底上形成绝缘膜和另一绝缘膜。 另一绝缘膜被回蚀刻以在绝缘膜的侧表面上形成侧壁间隔物。 然后，去除与第一和第二栅电极的侧壁相对应的绝缘膜的侧表面上的侧壁间隔物，以使侧壁间隔物超过对应于第三栅电极的侧壁的绝缘膜的侧表面。 然后，侧壁间隔物和绝缘膜被回蚀刻，使得侧壁间隔物由绝缘膜形成在第一，第二和第三栅电极的侧壁上。

公开(公告)号：US20230083989A1

公开(公告)日：2023-03-16

申请号：US17858555

申请日：2022-07-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/1159 ,  H01L27/11587 ,  H01L27/11592 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: Reliability of a semiconductor device including a ferroelectric memory is improved. A gate electrode of a ferroelectric memory is formed on a semiconductor substrate so as to arrange a ferroelectric film therebetween, and a semiconductor layer serving as an epitaxial semiconductor layer is formed on the semiconductor substrate on both sides of the gate electrode. The semiconductor layer is formed on a dent portion of the semiconductor substrate. At least a part of each of a source region and a drain region of the ferroelectric memory is formed in the semiconductor layer.

公开(公告)号：US20190312043A1

公开(公告)日：2019-10-10

申请号：US16362064

申请日：2019-03-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/28 ,  H01L29/792 ,  H01L29/78

Abstract: Provided is an inexpensive high-performance split gate MONOS memory. In a manufacturing process of a split gate MONOS memory, a protective layer is formed in an upper part of a control gate electrode before metal substitution of a memory gate electrode.

公开(公告)号：US20180138318A1

公开(公告)日：2018-05-17

申请号：US15867681

申请日：2018-01-10

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L29/792 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor substrate including a main surface, an element separation film formed over the main surface, and a fin protruding from the element separation film and extending in the first direction in plan view. The semiconductor device further includes a control gate electrode extending in the second direction that is orthogonal to the first direction along the surface of the fin through a gate insulating film and overlaps with a first main surface of the element separation film, and a memory gate electrode extending in the second direction along the surface of the fin through an insulating film and overlaps with a second main surface of the element separation film, in which the second main surface is lower than the first main surface relative to the main surface.

公开(公告)号：US20170352675A1

公开(公告)日：2017-12-07

申请号：US15582911

申请日：2017-05-01

Applicant: Renesas Electronics Corporation

Inventor： Tatsuyoshi MIHARA

IPC: H01L27/11568 ,  H01L29/78 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/11575 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/42344 ,  H01L29/42368 ,  H01L29/7851 ,  H01L29/7855 ,  H01L29/792

Abstract: To improve reliability of a semiconductor device, a control transistor and a memory transistor formed in a memory cell region are configured to have a double-gate structure, and a transistor formed in a peripheral circuit region is configured to have a triple-gate structure. For example, in the memory transistor, a gate insulating film formed by an ONO film is provided between a memory gate electrode and sidewalls of a fin, and an insulating film (a stacked film of a multilayer film of an insulating film/an oxide film and the ONO film) thicker than the ONO film is provided between the memory gate electrode and a top surface of the fin. This configuration can reduce concentration of an electric field onto a tip of the fin, so that deterioration of reliability of the ONO film can be prevented.