公开(公告)号：US20150076511A1

公开(公告)日：2015-03-19

申请号：US14550118

申请日：2014-11-21

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro OKAMOTO ,  Yuji ANDO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Kazuki OTA

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/201

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1−zAlzN (0≦z≦1), a channel layer having a composition of: AlxGa1−xN (0≦x≦1) or InyGa1−yN (0≦y≦1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.

Abstract translation: 场效应晶体管包括衬底和设置在衬底上的半导体层，其中半导体层包括设置在衬底上的下阻挡层，生长Ga面，晶格弛豫并具有组成In 1-z Al z N（0＆nl; z＆nl E; 1），具有以下组成的沟道层：Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）或In y Ga 1-y N（0＆nlE; y＆nlE; 1）。 或提供在栅极绝缘膜上并与栅极绝缘膜配置的栅电极，栅极配置在栅极绝缘膜上，栅电极配置在栅极绝缘膜上， 位于源电极和漏电极之间的区域。

公开(公告)号：US20140264274A1

公开(公告)日：2014-09-18

申请号：US14198430

申请日：2014-03-05

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Ryohei NEGA ,  Masaaki KANAZAWA ,  Takashi INOUE

IPC: H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/7787

Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.

Abstract translation: 提高半导体器件的性能。 例如，假设超晶格层被插入在缓冲层和沟道层之间，则导入形成超晶格层的一部分的氮化物半导体层中的受主的浓度高于形成氮化物半导体层的受主的浓度 超晶格层的另一部分。 也就是说，导入具有小带隙的氮化物半导体层的受主的浓度高于导入具有大带隙的氮化物半导体层的受主的浓度。

公开(公告)号：US20140209980A1

公开(公告)日：2014-07-31

申请号：US14229645

申请日：2014-03-28

Applicant: Renesas Electronics Corporation

Inventor： Takashi INOUE ,  Tatsuo NAKAYAMA ,  Yasuhiro OKAMOTO ,  Hironobu MIYAMOTO

IPC: H01L29/778 ,  H01L29/66

CPC classification number: H01L29/778 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/432 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783

Abstract: A method for manufacturing a semiconductor device includes forming a buffer layer made of a nitride semiconductor, forming a channel layer made of a nitride semiconductor over the buffer layer, forming a barrier layer made of a nitride semiconductor over the channel layer, forming a cap layer made of a nitride semiconductor over the barrier layer, forming a gate insulating film so as to in contact with the cap layer; and forming a gate electrode over the gate insulating film, wherein compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer by controlling compositions of the cap layer, the barrier layer, the channel layer, and the buffer layer.

Abstract translation: 一种半导体器件的制造方法，包括：形成由氮化物半导体构成的缓冲层，在所述缓冲层上形成由氮化物半导体构成的沟道层，在所述沟道层上形成由氮化物半导体构成的阻挡层，形成覆盖层 由阻挡层上的氮化物半导体形成，形成栅极绝缘膜以与盖层接触; 以及在所述栅极绝缘膜上形成栅电极，其中在所述覆盖层和所述阻挡层之间的界面处产生压缩应变，以及在所述沟道层和所述缓冲层之间的界面处产生压应变，并且在所述栅极之间的界面处产生拉伸应变 层和沟道层，通过控制盖层，阻挡层，沟道层和缓冲层的组成。

公开(公告)号：US20210135018A1

公开(公告)日：2021-05-06

申请号：US17121143

申请日：2020-12-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Kenichi HISADA

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417 ,  H01L29/16 ,  H01L29/47

Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

公开(公告)号：US20200161480A1

公开(公告)日：2020-05-21

申请号：US16598832

申请日：2019-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasuhiro OKAMOTO ,  Nobuo MACHIDA ,  Kenichi HISADA

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/08 ,  H01L29/47 ,  H01L29/417 ,  H01L29/16 ,  H01L29/66

Abstract: In a Schottky barrier diode region, a Schottky barrier diode is formed between an n-type drift layer and a metal layer, and in a body diode region, a p-type semiconductor region, a p-type semiconductor region, and a p-type semiconductor region are formed in order from a main surface side in the drift layer, and a body diode is formed between the p-type semiconductor region and the drift layer. An impurity concentration of the p-type semiconductor region is decreased lower than the impurity concentration of the p-type semiconductor regions, thereby increasing the reflux current flowing through the Schottky barrier diode and preventing the reflux current from flowing through the body diode.

公开(公告)号：US20190006500A1

公开(公告)日：2019-01-03

申请号：US15985987

申请日：2018-05-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takehiro UEDA ,  Yasuhiro OKAMOTO

IPC: H01L29/778 ,  H01L29/66 ,  H01L21/308 ,  H01L21/265

CPC classification number: H01L29/7783 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/308 ,  H01L29/402 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786

Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a sequential stack of a buffer layer, a channel layer, and a barrier layer, and includes a mesa part including a fourth nitride semiconductor layer formed over the stack, and a side part formed on both sides of the mesa part and including a thin film part of the fourth nitride semiconductor layer. Generation of 2DEG is suppressed below the mesa part while being unsuppressed below the side part. In this way, the side part that disables the 2DEG suppression effect is provided on an end portion of the mesa part, thereby a distance from an end portion of the side part to the gate electrode is increased, making it possible to suppress leakage caused by a current path passing through an undesired channel formed between a gate insulating film and the mesa part.

公开(公告)号：US20180061983A1

公开(公告)日：2018-03-01

申请号：US15789191

申请日：2017-10-20

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US20170294538A1

公开(公告)日：2017-10-12

申请号：US15632663

申请日：2017-06-26

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Ichiro MASUMOTO ,  Yasuhiro OKAMOTO ,  Shinichi MIYAKE ,  Hiroshi KAWAGUCHI

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/20

CPC classification number: H01L29/7827 ,  H01L29/1066 ,  H01L29/1083 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

公开(公告)号：US20170186880A1

公开(公告)日：2017-06-29

申请号：US15363386

申请日：2016-11-29

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/30 ,  H01L29/20

CPC classification number: H01L29/78681 ,  H01L21/3006 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/66522 ,  H01L29/78

Abstract: A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.

公开(公告)号：US20160233211A1

公开(公告)日：2016-08-11

申请号：US14970627

申请日：2015-12-16

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao MIURA ,  Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO

IPC: H01L27/06 ,  H01L29/872 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

CPC classification number: H01L27/0629 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787 ,  H01L29/872 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/4846 ,  H01L2224/4903 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power transistor (Q3) and a cathode of a diode (D4), and further functioning as a drain of a power transistor (Q4) and an anode of a diode (D3). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series.

Abstract translation: 限制了半导体器件的开关波形的振铃。 例如，布置了互连（L5），其用作功率晶体管（Q3）的源极和二极管（D4）的阴极，并且还用作功率晶体管（Q4）的漏极和功率晶体管 二极管（D3）。 换句话说，串联在该功率晶体管上的功率晶体管和二极管形成在同一半导体芯片中; 并且另外用作功率晶体管的漏极的互连和用作二极管的阳极的互连彼此共同。 这种结构使得可以降低功率晶体管和彼此串联耦合的二极管之间的寄生电感。